44results about How to "Increase current channel" patented technology

A method of manufacturing three-dimensional semiconductor device, comprising the steps of: forming a stack structure of a plurality of a first material layers and a second material layers on a substrate in the memory cell region; etching said stack structure to form a plurality of trenches; forming channel layers in said plurality of trenches; performing annealing treatment to at least one surface of the channel layers to reduce the surface roughness and the interface state. In accordance with the three-dimensional semiconductor device manufacturing method of the present invention, the formation of interface states is depressed by introducing a dummy channel sacrificial layer for the interface treatment on the channel surface and back surface, and/or the channel surface roughness is reduced by introducing a buffer layer on the channel surface and back surface during the treatment, which can improve the channel carrier mobility, improve the channel current as well as the reliability of the memory cell.

The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.

The invention discloses an isolation N-type laterally diffused metal oxide semiconductor (NLDMOS) device. Two separate N-type deep well are formed on the P-type silicon substrate; left N-type deep well left portion is formed with a P-well; P-well left portion is formed with a P-type heavily doped region and an N-type heavily doped source miscellaneous areas; over the top and left-right portion of the N-type deep well P-well right portion formed with a gate oxide layer; N-type deep well with left and right P-type silicon N-type deep well between the top and right-left portion of the N-type deep well substrate above the field oxide is formed; the right N-type deep well right portion is formed with a drain terminal N-type heavily doped region; and a gate oxide layer over the top of the left part of the field oxide is formed with a gate polysilicon; P-type silicon substrate and the bottom of the field oxide Right N-type deep well formed in P-type implant drift region, the right of the P-type implant drift region as a staging interval shape. The invention also discloses a method for producing the isolated NLDMOS devices. The method can be isolated in ensuring NLDMOS device breakdown voltage does not decrease at the same time makes the device on-resistance is reduced.

An electrical connector which is provided with an insulating body and a plurality of power terminal pairs fixed to the insulating body, the insulating body has a base portion, a butt portion extendingforwardly from the base portion and a plurality of first terminal grooves extending in the front-rear direction, the power supply terminal pair is accommodated in a corresponding first terminal groove, and each of the power supply terminal pairs comprises two power supply terminals, each of the power supply terminals is provided with a retaining portion retained in the first terminal groove, A plurality of contact portions extending forward from one end of the retaining portion and a welding portion extending from the other end of the retaining portion are arranged in a row in the height direction of the contact portions of two power supply terminals in each pair of power supply terminals, and the plurality of contact portions of the two power supply terminals are alternately arranged inthe lateral direction and circularly. The electric connector of the invention can effectively improve the heating condition of a pair of power supply terminals.

The present invention relates to a laterally diffused metal oxide semiconductor field effect transistor with an RESURF (reduced surface field) structure. The laterally diffused metal oxide semiconductor field effect transistor includes a substrate, a gate, a source, a drain, a body region, a field oxide region which is located between the source and the drain, as well as a first well region and a second well region which are located on the substrate; a plurality of gate doped regions are arranged in the second well region below the gate; the polysilicon gate of the gate is of a multi-section structure; the sections of the polysilicon gate are separated from one another; the gate doped regions are arranged below gaps between the sections of the polysilicon gate; and each gate doped region is electrically connected with one of two sections of the polysilicon gate which are located at two sides of the gate doped region, wherein the one section of the polysilicon gate electrically connected with the gate doped region is adjacent to the source. According to the laterally diffused metal oxide semiconductor field effect transistor with the RESURF structure of the invention, the number of trench electrons is increased, and the electrons are accelerated a plurality of times during a process of flowing from the source to the drain, equivalently, and a trench electric field and trench current can be improved, and therefore, trench resistance is reduced, and on-resistance can be reduced.

The embodiment of the invention provides a control method and device of a three-dimensional memory and a storage medium. The method comprises the following steps: determining to carry out reading operation on a selected first word line; wherein the selected first word line is at least one of a plurality of word lines of the three-dimensional memory; applying a first voltage to the first word line,wherein the first voltage is used for conducting a memory cell tube on the first word line, the first voltage is higher than the second voltage, the second voltage is a voltage applied to other wordlines when it is determined that reading operation is performed on other word lines except the first word line; and the second voltage is used for conducting the memory cell tubes on the other word lines. According to the embodiment of the invention, when the first word line is read, the read conduction voltage on the first word line selected in the three-dimensional memory is increased to increase the current flowing through the memory cell tube on the first word line, so that the channel current in the three-dimensional memory is increased.

The invention discloses a junction field effect transistor. A channel region is arranged between two adjacent same-doped well regions, the channel region is doped through diffusion of the two adjacent well regions, and well regions with the opposite doping types are arranged above the channel region and used for longitudinal depleting the channel region. According to the junction field effect transistor, the doping concentration of the channel region can be reduced, the pinch-off voltage of the channel region is lowered, and thus the pinch-off voltage of the channel region can be adjusted, a small pinch-off voltage is obtained and extra cost does not need to be added. The width requirement of the channel region can be met just by adjusting the widths of the two adjacent same-doped well regions on the two sides of the channel region, and thus the channel current of the device can be adjusted; moreover, the channel current can be enlarged easily, and thus a large channel current is obtained. The invention further discloses a manufacturing method of the junction field effect transistor.

The invention discloses a manufacturing method of a 3D memory device. The manufacturing method comprises the steps: forming a laminated structure on a substrate, wherein the laminated structure comprises interlayer dielectric layers and interlayer sacrificial layers which are alternately stacked; forming a channel hole passing through the laminated structure; forming a functional layer and a channel layer in the channel hole; forming a doped layer covering the channel layer; and annealing the doped layer so as to enable impurities in the doped layer to enter the channel layer. According to themanufacturing method, doped impurities are provided for the channel layer through the doped layer, and low-concentration doping of the channel layer is realized, so that the influence on other electrical properties of the 3D memory device is reduced while the channel current is improved.

The invention discloses a single-time programmable memory that comprises basis, several separation configurations, the first transistor and the second transistor. The separation configurations are set on the basis to define the active area. Each of the separation configurations possesses depression to make the top surface of the separation configuration lower than the basis. The first transistor is set on the active area of the basis, and extends to the sidewall of the depression, the gate electrode of the first transistor is selecting gate electrode. The second transistor is set on the active area of the basis, serially connected with the first transistor. The gate electrode of the second transistor is float gate electrode which is block type and bestrides over the basis of the separation configurations, and extends to the sidewall of the depression.

The invention discloses an RSD-based pulse power supply module. The module comprises a main capacitor, a magnetic switch, an RSD, a charging power supply, a switch pipe, a pre-charge capacitor, a pre-charge inductor and a control module and is characterized in that the main capacitor, the magnetic switch, the RSD, the charging power supply, the switch pipe, the pre-charge capacitor and the pre-charge inductor are integrated in one PCB; and the RSD is fixed on the PCB by a surrounded copper foil. By integrating the RSD power switch, the charging power supply, the capacitor and the magnetic switch in the PCB, all elements work cooperatively and length of a wire is reduced, so stray parameters like parasitic inductance of the power supply is reduced; the rate of rise di/dt of on-state current of the RSD is increased; in addition, the surrounded copper foil is used for welding and fixing the RSD, thereby facilitating acceleration of heat radiation of the RSD and increasing of current channels on the PCB; and copper foil is capable of equally distributing current trends, so current carrying capacity of the pulse power supply module is improved.

The invention discloses a method for preventing a connection point of a cable lug and a knife switch from overheating during current carrying. The method is characterized in that a bypass conductive belt is arranged on the connection point of the cable lug and a knife switch type terminal board; and one end of the bypass conductive belt contacts the upper surface of the cable lug to form electrical connection, and the other end contacts the lower surface of the knife switch type terminal board form electrical connection. The method not only enlarges the contact area of the cable lug and the knife switch type terminal board but also increases current channels of connection point, thereby more uniformly distributing load current, reducing contact resistance and effectively preventing the connection point of the cable lug and the knife switch from overheating in the process of current carrying operation. The invention has the advantages of simple method, easy manufacture of the bypass conductive belt, no change of the original structure of electrical equipment during construction and convenient field construction.

The embodiment of the invention provides a dual-grid three-dimensional storage device and a fabrication method thereof. The three-dimensional storage device comprises a TSG and a storage unit, whereintwo channels are formed in the three-dimensional storage device, a doping plug is formed on each channel, a grid structure is arranged between the two doping plugs, and the doping plugs are isolatedby the grid structure. In the three-dimensional storage device, the doping plug is arranged on each channel, thus, the current resistance can be reduced, and the current passage is improved; by increasing the number of the doping plug, only a TSG is needed, and the problem of excessively large threshold voltage amplitude generated between two TSGs is prevented; the current passage is improved, thus, no boron is injected into the channels, and the problem of threshold value interference generated by the storage device caused by high-concentration doping is further prevented; and moreover, sincethe three-dimensional storage device only comprises the TSG, the density of the storage unit can be improved.