Three-dimensional semiconductor device and fabrication method thereof

Abstract

A three-dimensional semiconductor device comprises a plurality of storage units. Each storage unit comprises a channel layer, a bottom grid conductive layer, a floating gate layer, a plurality of second insulation layers, a plurality of grid conductive layers, a grid dielectric layer, a drain and a source, wherein the channel layer is arranged in a direction perpendicular to the surface of a substrate; the bottom grid conductive layer is arranged in a first insulation layer stack and arranged on a side wall of the channel layer; the floating gate layer is arranged on the first insulation layer stack and arranged on the side wall of the channel layer; the plurality of second insulation layer and the plurality of grid conductive layer are arranged on the floating grid layer and alternatively stacked along the side wall of the channel layer; the grid dielectric layer is arranged on the side wall of the channel layer; the drain is arranged at the top of the channel layer; and the source is arranged in the substrate between adjacent two storage units of the plurality of storage units. A floating gate which is not led out is embedded into the three-dimensional semiconductor device, a voltage is induced on the floating gate through voltage coupling on a near leading-out grid, thus, silicon epitaxial growth (SEG) and channel inversion of a poly-silicon contact region are assistantly completed, the current bottleneck of the region is overcome, the channel current is increased, and the consistency of threshold voltages of a field effect transistor (FET) near to the floating gate is effectively controlled.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, as figure 1 As shown, a multi-layer stack structure (for example, multiple ONO structures alternat...

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Problems solved by technology

In addition, the threshold voltage of the dummy cell will be due to the asymmetric fringe electric field (FringeField, such as figure 1 Arrow) will make the threshold voltage too large, difficult to control

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