A three-dimensional
semiconductor device comprises a plurality of storage units. Each storage unit comprises a channel layer, a bottom grid conductive layer, a floating gate layer, a plurality of second insulation
layers, a plurality of grid conductive
layers, a grid
dielectric layer, a drain and a source, wherein the channel layer is arranged in a direction perpendicular to the surface of a substrate; the bottom grid conductive layer is arranged in a first
insulation layer stack and arranged on a side wall of the channel layer; the floating gate layer is arranged on the first
insulation layer stack and arranged on the side wall of the channel layer; the plurality of second
insulation layer and the plurality of grid conductive layer are arranged on the floating grid layer and alternatively stacked along the side wall of the channel layer; the grid
dielectric layer is arranged on the side wall of the channel layer; the drain is arranged at the top of the channel layer; and the source is arranged in the substrate between adjacent two storage units of the plurality of storage units. A floating gate which is not led out is embedded into the three-dimensional
semiconductor device, a
voltage is induced on the floating gate through
voltage coupling on a near leading-out grid, thus,
silicon epitaxial growth (SEG) and
channel inversion of a poly-
silicon contact region are assistantly completed, the current
bottleneck of the region is overcome, the channel current is increased, and the consistency of threshold voltages of a
field effect transistor (FET) near to the floating gate is effectively controlled.