Photo-etching method

Abstract

The invention discloses a lithography method, relating to the semiconductor manufacturing field and aiming at overcoming the defect of the traditional lithography method that the evenness of etched patterns is poor. The lithography method of the invention includes the following steps: a wafer to be processed is provided; photoresist is plated on the surface of an etched layer of the wafer and the thickness of the photoresist at the center of the wafer is different from that of the peripheral parts of the wafer; an exposure step is carried out; a development step is carried out; an etching step is carried out; and the remaining photoresist is removed. Compared with the prior art, the method can obtain a circuit pattern with better evenness and the unification for the etched patterns can be further controlled for the distortion states of position patterns on the wafer are identical and then the traditional methods such as the correction methods of optical approaching correction and exposure machine approaching correction, etc., can be conveniently adopted.

Description

technical field [0001] The invention relates to manufacturing technology in the field of semiconductors, in particular to a photolithography method for semiconductor devices. Background technique [0002] With the rapid development of semiconductor technology, semiconductor devices are becoming more and more sophisticated, which makes it more difficult for people to control process errors. The lithography process is an important link in the manufacture of semiconductor devices, and how to obtain a better critical dimension (CD) in the lithography process is becoming more and more important. [0003] The existing method of etching pattern is: at first at first the etched layer 1 surface of wafer is plated photoresist 2, and photoresist thickness is uniform, as figure 1 Shown; Then carry out developing step, if what adopt positive photoresist, then the photoresist of exposure area is removed; Then carry out etching step, etch out required circuit pattern on etched layer 2; p...

AI Technical Summary

Problems solved by technology

However, inspection after the etch step found that the graphic critical dimension uniformity is poor, such as image 3 As shown, the pattern CD variation in the center part of the wafer is smaller than that in the edge part

Using the existing method, the etching pattern and the required circuit pattern are quite different, and because the pattern distortion is different at different positions on the wafer, the traditional method such as optical approach correction and exposure machine approach correction is due to its The limitation of itself cannot make the etching pattern meet the requirements

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