Shower head of a wafer treatment apparatus having a gap controller

a technology of wafer treatment and shower head, which is applied in the direction of coating, chemical vapor deposition coating, metallic material coating process, etc., can solve the problems of inability to achieve uniform etching over the entire wafer surface, and inability to achieve uniform etching rate. optimum
US20050145338A1Inactive Publication Date: 2005-07-07SAMSUNG ELECTRONICS CO LTD

Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
SAMSUNG ELECTRONICS CO LTD
Publication Date
2005-07-07
Estimated Expiration
Not applicable · inactive patent

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Abstract

A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.
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Description

BACKGROUND OF-THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an apparatus for manufacturing a semiconductor device. More particularly, the present invention relates to a shower head provided to supply a reactant gas using plasma to a reaction chamber in a wafer treatment apparatus.

[0003] 2. Description of the Related Art

[0004] As the integration density of semiconductor devices increases, a design rule decreases and the diameter of a wafer increases. Large wafers often undergo multiple steps for fabricating semiconductor devices, including, for example, deposition processes for depositing material layers on a wafer or etch processes for etching material layers on the wafer in a predetermined pattern by supplying a reactant gas from the upper portion of a reaction chamber for depositing or etching the wafer. In particular, as wafer sizes increase, during etch processes, it is important to optimize uniformity in etch rates over the entire wafe...

Claims

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