1203results about How to "Reduced series resistance" patented technology

A relatively small ESD protection diode is formed on the same chip as a light emitting diode. In one embodiment, the ESD diode is a mesa-type diode isolated from the light emitting diode by a trench. To reduce the series resistance of the ESD diode, the PN junction and metal contact to the semiconductor material is made long and expands virtually the width of the chip. Various configurations of the PN junction and the N and P metal contacts for the ESD diode are described for increasing the breakdown voltage and for improved testing.

The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

The invention relates to a photoactive component, especially a solar cell, comprising organic layers and formed by at least one stacked pi, ni, and/or pin diode. The diodes are characterised in that they comprise at least one p-doped or n-doped transport layer having a larger optical band gap than that of the photoactive layer. The individual diodes are characterised by a high internal quantum yield, but can be optically thin (peak absorption <80%). A high external quantum yield is obtained by either enlarging the optical path of the incident light in the diodes using light traps, or by stacking a plurality of the diodes. The transition between two diodes being facilitated by transition layers for the purposes of improved recombination and generation. Both forms of embodiment have a number of specific advantages using the doped transport layers with a large band gap.

The present invention discloses through-hole vertical semiconductor devices and chips. The structure of an embodiment of through-hole vertical semiconductor devices and chips having static protection diodes is the following: a semiconductor epitaxial layer is bonded to the first surface of a supporting chip with static protection diode; the first-type cladding layer of the semiconductor epitaxial layer is electrically connected to a first electrode on the second surface of the supporting chip via a current spreading layer, a patterned electrode, a half-through-hole-metal-plug and a through-hole-metal-plug; the second-type cladding layer of the semiconductor epitaxial layer is electrically connected to a second electrode on the second surface of the supporting chip via a reflector/Ohmic/bonding layer and at least one through-hole-metal-plug. An external power source is electrically connected to the first and second electrodes without wire bonding.

A field effect transistor includes: a first nitride semiconductor layer having a plane perpendicular to a (0001) plane or a plane tilted with respect to the (0001) plane as a main surface; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; and a source electrode and a drain electrode formed so as to contact at least a part of the second nitride semiconductor layer or the third nitride semiconductor layer. A recess that exposes a part of the second nitride semiconductor layer is formed between the source electrode and the drain electrode in the third nitride semiconductor layer. A gate electrode is formed in the recess and an insulating film is formed between the third nitride semiconductor layer and the gate electrode.

The invention provides a lead-free silver conductive paste used for positive electrode of solar battery and a preparation technique thereof. The paste comprises the following materials by weight percentage: 65 to 85 percent of silver powder, 2 to 8 percent of lead-free glass powder, 10 to 25 percent of organic carrier and 0.1 to 3 percent of additive. The paste adopts the lead-free glass powder of Si-B-Bi-Al-Ti-Zn-O series to replace the traditional lead-bearing glass powder; and the series glass powder has lower softening point, can lead the silver electrode to have good adhesive force after sintering, and ensures the silver electrode to be well contacted with a silicon substrate. In addition, zinc resinate is used as the additive in the invention, not only can well improve the printing performance of the paste, but also can improve the electrical property of the electrode.

Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

The invention discloses a process for manufacturing a solar cell by twice screen printing and grooving, which is used for manufacturing the solar cell by twice electrode printing and comprises a grooving process and a twice printing process, wherein the grooving process comprises the step of performing grooving on an electrode grid line area on the surface of a silicon wafer so as to form an etched groove in the electrode grid line area; and the twice printing process comprises the following steps of: a, primary electrode printing, namely, filling printing electrode paste into the etched groove and performing drying to form a first layer of electrode in the etched groove; and b, secondary electrode printing, namely, printing the electrode on the outer surface of the first layer of electrode so as to form a second layer of electrode in the electrode grid line area on the surface of the silicon wafer. The solar cell manufactured by the method has relatively lower series resistance, a selective emitter and relatively higher conversion efficiency, and can reduce shading loss; and the electrode paste is difficult to spread in a sintering process.

The present invention relates to the field of solar cells, and in particular to a main-gate-free and high-efficiency back-contact solar cell module, a main-gate-free and high-efficiency back-contact solar cell assembly, and a preparation process thereof. The solar cell module, comprising cells and an electrical connection layer, a backlight side of the cells having P-electrodes connected to a P-type doping layer and N-electrodes connected to a N-type doping layer, is characterized in that the electrical connection layer comprises a number of parallel leads each electrically connected to the P-electrodes or the N-electrodes. The present invention has the beneficial effect that a main-gate-free and high-efficiency back-contact solar cell module, a main-gate-free and high-efficiency back-contact solar cell assembly, and a preparation process thereof are provided, which can effectively the short-circuiting of the P-electrodes and the N-electrodes and has the advantages of low cost, high hidden-cracking resistance, high efficiency and high stability.