867 results about "Electrode Grid" patented technology

A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source / drain (S / D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S / D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S / D electrodes which are separated from the gate protection layer by the first passivation layer.

The invention discloses a back contact solar cell, an assembly and a photovoltaic system, and relates to the field of silicon solar cells. The back contact solar cell comprises a silicon substrate, a first doping layer, a second doping layer, a positive electrode grid line, a negative electrode grid line and a first PAD part. The first doping layers and the second doping layers are alternately arranged along a first direction; the first doped layer comprises a first sub-doped layer, and the second doped layer comprises a second sub-doped layer adjacent to the first sub-doped layer; the second doping sub-layer and the first doping sub-layer form an electric leakage composite contact structure at a preset position; the positive grid line comprises a first sub-positive grid line arranged on the first sub-doping layer, and the negative grid line comprises a first sub-negative grid line arranged on the second sub-doping layer; each group of first PAD parts comprises a first PAD point and a second PAD point, the first PAD point is electrically connected with the first sub positive grid line, and the second PAD point is electrically connected with the first sub negative grid line. By implementing the method, the hot spot effect can be accurately represented at the battery end.

The invention belongs to the technical field of semiconductors, and particularly discloses a depletion type GaN device and a preparation method thereof.The depletion type GaN device comprises a source electrode, a drain electrode, a gate electrode, a plurality of gate structures, a field plate unit, a gate connecting assembly, a field plate connecting assembly, a gate driving resistor, a field plate driving resistor, a first dielectric layer and a second dielectric layer; the field plate unit comprises a plurality of field plates; one end of each of the plurality of gate structures is electrically connected with one end of the gate connecting assembly, and the other end of the gate connecting assembly is electrically connected with one end of the gate driving resistor; one end of each of a plurality of field plates of the field plate unit is connected with one end of the field plate connecting assembly, and the other end of the field plate connecting assembly is electrically connected with one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel with the gate electrode. According to the depletion type GaN device, the gate structure and the field plate unit are respectively provided with respective driving loops, so that voltage division adjustment is facilitated.

The utility model discloses a solar cell and a photovoltaic assembly, the surface of a substrate of the solar cell is provided with a plurality of grid line electrodes, each grid line electrode comprises a plurality of fine grid lines arranged at intervals along a first direction, and the polarities of two adjacent fine grid lines are opposite; the fine grid lines are provided with conductive connecting parts; along the first direction, the plurality of conductive connection parts of the plurality of fine grid lines with the same polarity form conductive connection groups, and the plurality of columns of conductive connection groups are arranged at intervals along the second direction; the solar cell further comprises a plurality of insulating pieces covering the area where the conductive connecting sets are located, and gaps exist between the insulating pieces and the conductive connecting parts. In the thickness direction of the substrate, the thickness of the insulating part is smaller than that of the conductive connecting part. The thickness of the insulating part is lower than that of the conductive connecting part, so that the possibility that the welding strip is influenced by the insulating part when being connected with the conductive connecting part is reduced, and the overall working efficiency of the solar cell is improved.

The invention discloses a photovoltaic electrode grid line preparation method and a photovoltaic cell, and relates to the technical field of photovoltaic cells. The preparation method of the photovoltaic electrode grid line comprises the following steps: providing a preset mold which is complementary with an electrode pattern to be embossed and formed in shape; preparing a required polymer layer on the mold according to preset process parameters, and taking the required polymer layer as a transfer printing substrate; coating the forming side of the polymer layer with conductive slurry which at least can fill the grooves in the polymer layer, and removing redundant conductive slurry on the surface of the polymer layer, so that the surfaces of the grooves and the conductive slurry are located on the same plane; a required polymer layer is prepared on a mold according to preset process parameters and serves as a transfer printing substrate, and then the polymer layer is subjected to transfer printing, dissolution and other processes, so that precise and high-resolution electrode grid line preparation is realized on a base material, mold damage caused by repeated impressing and demolding is solved, and the production efficiency is improved. And the service life of the die is shortened.

The invention discloses a back contact solar cell, a cell string, an assembly and a photovoltaic system, and relates to the field of silicon solar cells. The back contact solar cell comprises a silicon substrate, a first doping layer, a second doping layer, a positive electrode grid line, a negative electrode grid line, a first test point and a second test point. The second doping layer is in composite contact with the first doping layer at a preset position to form an electric leakage composite contact structure; the first test point comprises a first test PAD point and a second test PAD point, the first test PAD point is electrically connected with the positive grid line, and the second test PAD point is electrically connected with the negative grid line. The second test point comprises a third test PAD point and a fourth test PAD point, the third test PAD point is electrically connected with the positive grid line, and the fourth test PAD point is electrically connected with the negative grid line. By implementing the embodiment, the characterization of the hot spot resistance effect can be realized at the battery end.

The invention discloses a composite conductive paste transfer film, a photovoltaic electrode grid line preparation method and a photovoltaic cell, and relates to the technical field of photovoltaic cells. According to the preparation method of the composite conductive slurry transfer printing film, high-precision impressing forming, transfer printing, dissolving and other technologies are adopted for a PVA film, and composite conductive slurry is adopted, so that precise electrode design is achieved on a crystal silicon wafer. The high-precision impressing technology and the transfer printing technology are applied to preparation of the photovoltaic electrode grid line, and the precision and the resolution ratio of the electrode grid line can be greatly improved. Compared with a traditional single silver paste grid line, the use amount of silver paste can be reduced and the industrial cost can be reduced on the basis of achieving higher photoelectric conversion efficiency by using the composite conductive paste. The PVA film with proper thickness and hardness is directly used as a substrate to complete transfer printing, a conventional complex structure of a transfer printing substrate film and a water-soluble polymer coating is replaced, and the problems that the silicon wafer is damaged and the grid line structure is influenced due to the fact that the subsequent substrate cannot be easily separated from the crystal silicon wafer can also be solved.

The invention relates to a preparation method of an electrode grid line and a photovoltaic cell, and relates to the field of photovoltaic technology, and the preparation method comprises the following steps: S1, providing a substrate, and forming a polymer layer on the substrate; s2, pressing a groove corresponding to a required electrode pattern on the polymer layer by using a mold to obtain a template; s3, a conductive material is smeared on the polymer layer, the groove is filled with the conductive material, and the redundant conductive material is scraped off; s4, providing a base material, covering the base material with the template, and transferring the polymer layer and the conductive material to the base material at a certain temperature and pressure; s5, stripping the substrate from the polymer layer, dissolving the polymer layer, and leaving the conductive material to be adhered to the base material; and S6, sintering the conductive material to form the electrode grid line. According to the invention, plate coating, high-precision transfer printing, water dissolution and high-temperature sintering technologies are utilized, the production process is efficient, and the accuracy of electrode patterns can be maintained.

The invention relates to a solar cell and a preparation method and application thereof.The solar cell comprises a silicon substrate, the silicon substrate is provided with a light receiving face and a backlight face which are arranged back to back, the surface of the backlight face comprises a laminated structure and a negative electrode grid line arranged on the surface of the laminated structure, the backlight face comprises at least one groove, and the negative electrode grid line is arranged in the groove. A groove is formed in the light receiving surface, the negative grid line is arranged in the groove, a first suede surface is formed on the inner wall of the groove, a second suede surface is formed on the light receiving surface, and the density of the first suede surface is smaller than that of the second suede surface in unit area. The solar cell provided by the invention not only can realize efficiency maximization, but also has excellent reliability.

A semiconductor device includes a substrate including an active pattern, a channel pattern and a source / drain pattern on the active pattern wherein the channel pattern includes semiconductor patterns vertically stacked and spaced apart from each other, the plurality of semiconductor patterns including a first semiconductor pattern and a neighboring second semiconductor pattern, and a gate electrode on the semiconductor patterns. The gate electrode includes an inner electrode between the first and second semiconductor patterns. The source / drain pattern includes a buffer layer and a main layer on the buffer layer. An indent region is defined in a vertical cross section of the device by the main layer, the first and second semiconductor patterns, and the inner electrode. The buffer layer is in the indent region. The buffer layer does not extend onto sidewalls of the first and second semiconductor patterns.

A semiconductor device includes an insulating substrate, a silicon layer on the insulating substrate, a dopant layer on the silicon layer, a buried spacer on a side surface of the dopant layer, a channel pattern on the dopant layer, the channel pattern comprising a plurality of semiconductor patterns vertically stacked and spaced apart from each other, a source / drain pattern on the buried spacer, the source / drain pattern connected to the channel pattern, a gate electrode on the channel pattern, the gate electrode comprising a plurality of inner electrodes between the semiconductor patterns, respectively, a lower power interconnection line in a lower portion of the insulating substrate, and a backside contact extending into the insulating substrate and the silicon layer to electrically connect the lower power interconnection line to the source / drain pattern. A side surface of the backside contact is in contact with the silicon layer and the buried spacer.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a high-heat-dissipation GaN nanowire radio frequency device and a preparation method thereof.The radio frequency device comprises a heterogeneous bonding substrate, a bonding middle layer, an AlGaN / GaN nanowire (a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a GaN cap layer), a passivation layer and an electrode layer, and the electrode layer comprises a source electrode, a gate electrode and a drain electrode; the passivation layer covers the gaps between the nanowires through front deposition, so that the preparation of the high-heat-dissipation nanowire transistor is realized, and the problem that the linearity of the device is reduced due to a self-heating effect is solved; holes are formed in the grid electrode, the thickness of the passivation layer on each nanowire is controlled, equal difference distribution is achieved, the linearity of the device is improved through the transconductance compensation effect, the grid voltage swing of the radio frequency device can be effectively improved, and therefore the available range of the device is greatly widened.

A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

The invention discloses a back contact solar cell, an assembly and a photovoltaic system, and relates to the field of silicon solar cells. Specifically, the back contact solar cell comprises a silicon substrate, a first doping layer, a second doping layer, a positive electrode grid line, a negative electrode grid line and a first PAD part. The second doping layer is in composite contact with the first doping layer at a preset position to form an electric leakage composite contact structure; each group of first PAD parts comprises a first PAD point and a second PAD point, the first PAD point is electrically connected with at least one positive grid line, and the second PAD point is electrically connected with at least one negative grid line; the positive grid line electrically connected with the first PAD point extends along a second direction, and the extension distance is l1; the distance between the first edge and the second edge is L, and l1 / L is greater than or equal to 0.9; the negative grid line electrically connected with the second PAD point extends along a second direction, and the extension distance is l2; l2 / L > = 0.9. By implementing the method, the hot spot effect can be accurately represented at the battery end.

The present disclosure relates to the technical field of display chips. Disclosed are a full-color MicroLED and a manufacturing method therefor. The full-color MicroLED comprises a driving substrate, a first light-emitting layer, a first connecting layer, a second light-emitting layer, and a second connecting layer; the driving substrate comprises a first P-type semiconductor electrode transition layer; the first light-emitting layer comprises first light-emitting units and a second P-type semiconductor electrode transition layer; the first connecting layer comprises a first N-type semiconductor electrode transition layer, first N-electrode grids, and a third P-type semiconductor electrode transition layer; the second light-emitting layer comprises second light-emitting units and a fourth P-type semiconductor electrode transition layer; the second connecting layer comprises a second N-type semiconductor electrode transition layer and second N-electrode grids; a color conversion layer is provided at the position of the second connecting layer corresponding to some of the second light-emitting units. In the present disclosure, the driving substrate drives the light-emitting units on the first light-emitting layer and the second light-emitting layer to respectively emit green light and blue light, and then part of the blue light of the second light-emitting units is converted into red light by means of the color conversion layer, thereby achieving full-color light emission.

The invention relates to a high-precision and high-resolution solar cell grid line preparation method. According to the method, a direct photoetching technology is adopted, accurate exposure is carried out on a photosensitive adhesive layer through a high-precision designed shading mask, and a patterned opening which is completely consistent with the layout of a grid line on the surface of a solar cell is formed. And then, accurately filling conductive slurry into the opening by using a coating or ink-jet printing technology, removing redundant slurry through mechanical scraping or chemical cleaning, and forming a stable grid line structure with excellent conductivity after high-efficiency grid line forming technical treatment such as drying and laser irradiation or high-temperature heat treatment. According to the scheme, the detail precision and the resolution ratio of the electrode grid line are improved, finer pattern preparation is achieved, the accuracy of the size of the grid line is ensured by accurately controlling the thickness of the photosensitive adhesive layer and the width of the patterning opening, and the overall performance and the photoelectric conversion efficiency of the solar cell can be improved. According to the preparation method, the technological process is simplified, and the production efficiency is improved.

The invention provides a photovoltaic cell grid line preparation method and device, and the method comprises the steps: obtaining a to-be-manufactured piece of a grid line, and the to-be-manufactured piece of the grid line is a photovoltaic cell semi-finished product containing a dielectric layer before the electroplating of the grid line; the grid line to-be-manufactured piece is subjected to film opening, a strip-shaped conductive area from one side of the grid line to-be-manufactured piece to the other side of the grid line to-be-manufactured piece is formed, and the conductive area is used for being connected with an external electrode; patterning the to-be-manufactured piece of the grid line after the film is opened, and removing the dielectric layer of the to-be-manufactured piece of the grid line to form a contact area of the grid line; and preparing the grid line in the contact area through an electroplating process, connecting the conductive area on the to-be-manufactured piece of the grid line to an external electrode when the grid line is electroplated, and horizontally placing the to-be-manufactured piece of the grid line and making contact with the electroplating liquid. The metal grid line prepared by the method is more uniform in height and better in pulling-out force, a seed layer does not need to be prepared, the production cost is reduced, and the preparation time is shortened.

A photovoltaic module with a hidden bus bar is provided and comprises battery strings, the battery strings are a plurality of battery pieces connected in series in the X direction, and the plurality of battery strings are arranged in the Y direction; the battery pieces comprise positive electrode grid lines and negative electrode grid lines which are alternately arranged and are connected through positive electrode welding strips and negative electrode welding strips, and the battery pieces in the battery strings are connected through the positive electrode welding strips or the negative electrode welding strips; the bus bars are arranged along the Y direction and are connected with two adjacent battery strings; the bus bar comprises a bus bar main body and a plurality of extension parts which are arranged at intervals along the extension direction of the bus bar main body and are perpendicular to the main body, the extension parts are positioned on one side or two sides of the bus bar main body, and one ends of the extension parts extend out of the bus bar main body and are arranged above the first welding strip to be welded with the first welding strip; the insulating layer is arranged below the bus bar and is arranged on the second welding strip below the bus bar; wherein the first welding strip is a welding strip which is directly connected and welded with the bus bar, and the second welding strip is a welding strip which is not directly connected and welded with the bus bar. The photovoltaic module provided by the utility model does not have a sealing-off problem.

The invention relates to an electrode grid line preparation method and a photovoltaic cell, and relates to the field of photovoltaic technology, and the method comprises the following steps: S1, providing a substrate, and forming a polymer layer on the substrate; s2, providing a first mold, and pressing a first groove on the polymer layer; s3, first conductive slurry is smeared on the polymer layer; s4, providing a second mold, and pressing a second groove on the first conductive slurry; s5, smearing second conductive slurry on the first conductive slurry; s6, providing a base material, and transferring the first conductive slurry and the second conductive slurry onto the base material; s7, stripping the substrate, dissolving the polymer layer, and enabling the first conductive slurry and the second conductive slurry to be adhered to the base material; and S8, sintering the first conductive slurry and the second conductive slurry to form the electrode grid line. By adopting a combined structure of the first conductive slurry and the second conductive slurry, the cost can be reduced while the conductive effect of the electrode grid line is improved.

The invention belongs to the technical field of power semiconductors, and discloses a substrate voltage regulation GaN HEMT power device which comprises a P substrate, a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, a passivation layer and a floating field plate structure which are sequentially stacked from bottom to top in the vertical direction of the device. A source electrode, a gate structure and a drain electrode which are not in contact with one another are sequentially arranged on the surface of the AlGaN barrier layer in the transverse direction of the device; the floating field plate structure comprises a plurality of floating field plates which are not in contact with one another, the P substrate is connected with any one field plate in the floating field plate structure through metal, so that the potential of the P substrate is the same, the voltage of the floating field plate can regulate and control the voltage of the substrate, high voltage resistance is realized, and dynamic resistance degradation is inhibited. The method has the advantages that under the condition that on resistance is not increased, high voltage resistance is achieved, collapse of a dynamic resistor is restrained, additional process steps are not increased, the area of a chip is not increased additionally, and cost is saved.

A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.

The invention discloses a crystalline silicon cell module, a preparation method and a photovoltaic system, and belongs to the technical field of solar cells. The crystalline silicon battery assembly comprises a plurality of crystalline silicon battery pieces, the plurality of crystalline silicon battery pieces comprise a first crystalline silicon battery piece and a second crystalline silicon battery piece, the light facing surface of the first crystalline silicon battery piece is provided with a first connecting piece, and the backlight surface of the second crystalline silicon battery piece is provided with a second connecting piece; the first connecting piece comprises a first electrode grid line, the first electrode grid line is electrically connected with the light-facing surface of the first crystalline silicon battery piece, the second connecting piece comprises a second electrode grid line, the second electrode grid line is electrically connected with the backlight surface of the second crystalline silicon battery piece, and the first connecting piece and the second connecting piece extend in opposite directions so as to be connected with each other; and the first electrode grid line is in contact connection with the second electrode grid line. The electrode grid lines between the two crystal silicon battery pieces are directly connected, so that no welding strip is needed for connection, the shading influence caused by the welding strip can be avoided, and the power of the module is improved.

The invention discloses a battery microstructure three-dimensional reconstruction simulation method and system based on an electrochemical model and computer equipment. The method comprises the following steps: acquiring a lithium ion battery electrode scanning sequence image, and acquiring a three-dimensional voxel model and an electrode grid chart; s2, acquiring key microstructure parameters of the electrode; s3, performing mesh generation on three-phase voxels in the electrode mesh chart to obtain a mesh file for finite element calculation; and S4, comparing the experimental data of the battery with the simulation data of the three-dimensional microstructure electrochemical model, adjusting the precision of the three-dimensional microstructure electrochemical model, and optimizing related parameters. According to the invention, three-phase accurate segmentation is carried out by using filtering and denoising, image enhancement and connectivity and a watershed segmentation algorithm, and a three-dimensional voxel model containing real particle morphology, cracks and pores and an electrode grid chart are reconstructed; the problems that in the prior art, a lithium ion battery microstructure simulation model is large in idealization deviation and inconsistent with a real structure, and consequently performance prediction is inaccurate are solved.

A semiconductor device includes a cell array region and a contact region; a gate stack structure groups of gate electrodes; a channel structure extending through the gate stack structure in the cell array region; and gate contact portions connected to respective gate electrodes in the contact region. At least some of the gate contact portions extend through a through gate electrode connected to a connection gate electrode at a lower end portion. The gate contact portions include contact groups extending from a first side to a second side of the gate electrodes in an extending direction. Each of the electrode groups includes an upper group on a lower group. Each of the contact groups includes a first group connected to the upper group and a second group on the second side in the extending direction, and connected to the lower group, and a number of layers of the connection gate electrodes to which the gate contact portions are connected sequentially increases as a distance from a boundary between the first group and the second group increases in the first group and the second group.

A semiconductor device comprising a first lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction, a first and second plurality of nanosheets stacked apart from one another in a vertical direction, a first gate electrode extending in a second horizontal direction, the first gate electrode surrounding the first plurality of nanosheets, a second gate electrode extending in the second horizontal direction, the second gate electrode surrounding the second plurality of nanosheets, a source / drain region between the first and second gate electrodes, a source / drain contact penetrating the first lower interlayer insulating layer and the insulating pattern, the source / drain contact electrically connected to the source / drain region, and a gate contact penetrating the first lower interlayer insulating layer and the insulating pattern, the gate contact electrically connected to the second gate electrode, at least a portion of a sidewall of the gate contact contacting the source / drain contact.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut is confined within the gate trench such that it does not extend beyond the walls of the gate trench as defined by gate spacer structures. Additionally, the gate dielectric does not form on any surface of the gate cut, such that the gate cut directly contacts the gate electrode.

The invention discloses a preparation method of a TBC battery electrode grid line, the electrode grid line and a TBC battery, and belongs to the technical field of solar cells, and the preparation method comprises the following steps: carrying out double-sided polishing on a silicon wafer; sequentially depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon wafer, and performing boron diffusion; digging an N region and a PN connection partition region on the back surface of the silicon wafer; sequentially depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon wafer, and performing phosphorus diffusion on the basis of the tunneling oxide layer and the intrinsic polycrystalline silicon layer; digging a P region and a GAP region on the back surface of the silicon wafer, and digging a hole channel by using a second laser; removing the borosilicate glass layer and the phosphorosilicate glass layer in the pore channel area; sequentially depositing an aluminum oxide layer and a silicon nitride layer on the surface of the silicon wafer; printing non-burn-through slurry in the main grid areas of the P area and the N area through the silk screen printing plate; and carrying out laser-assisted sintering on the auxiliary grid line pore channel region. The completeness of a passivation film layer structure on the back surface of the battery piece is ensured, meanwhile, the contact area of a metal electrode and a silicon substrate is reduced, and metal contact recombination is effectively reduced.

The invention provides a solar cell and a preparation method thereof, and a photovoltaic module, the solar cell comprises a silicon substrate, and the back surface of the silicon substrate comprises first doped regions and second doped regions which are alternately arranged along the horizontal direction of the silicon substrate; the first doped region comprises a P-type doped layer, the back surface of the P-type doped layer is provided with an electrode grid line, and the doping concentration of the first doped region is 1 * 10 < 17 > atom / cm < 3 > to 1 * 10 < 19 > atom / cm < 3 >; the second doped region comprises an N-type doped layer, the back surface of the N-type doped layer is provided with an electrode grid line, and the doping concentration of the second doped region is 1 * 10 < 17 > atom / cm < 3 > to 1 * 10 < 19 > atom / cm < 3 >; and the first passivation layer is positioned on the surfaces of the P-type doped layer and the N-type doped layer. According to the invention, the structural complexity of the solar cell is reduced, and the yield of the solar cell is improved.

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source / drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

The present disclosure provides a solar cell, a module and a system. The solar cell comprises a silicon substrate, first doped layers, second doped layers, positive electrode grid lines, negative electrode grid lines and a first PAD portion. The second doped layers are in recombination contact with the first doped layers at predetermined positions, so as to form leakage recombination contact structures. A first PAD point and a second PAD point of the first PAD portion are electrically and respectively connected to at least one positive electrode grid line and at least one negative electrode grid line.