768 results about "Electrode Grid" patented technology

A proximity-based mutually capacitance-sensitive touchpad that is disposed directly beneath a keypad keymat of a mobile telephone, wherein posts associated with each key pass through a mutually capacitance-sensitive sensor electrode grid of the touchpad such that the keypad posts do not interfere with touchpad detection and tracking of a pointing object that moves along the keypad surface, to thereby enable touchpad data entry, cursor control, and scroll bar control on a display of the mobile telephone, wherein the keypad posts actuate mechanical switches underneath the touchpad.

In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

One embodiment of the present invention provides a method for fabricating solar cells. During operation, an anti-reflection layer is deposited on top of a semiconductor structure to form a photovoltaic structure, and a front-side electrode grid comprising a metal stack is formed on top of the photovoltaic structure. The metal stack comprises a metal-adhesive layer comprising Ti or Ta, and a conducting layer comprising Cu or Ag situated above the metal-adhesive layer.

One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

An optoelectronic device comprising at least one nanostructure-film electrode is discussed. The optoelectronic device may further comprise a different material, such as a polymer, to fill pores in the nanostructure-film. Additionally or alternatively, the optoelectronic device may comprise an electrode grid superimposed on the nanostructure-film.

A solar cell comprising at least one nanostructure-film electrode is discussed. The solar cell may further comprise a different conducting material, such as a conducting polymer, to fill pores in the nanostructure-film. Additionally or alternatively, the solar cell may comprise an electrode grid superimposed on the nanostructure-film. Likewise, the solar cell may have a single or multiple active layer(s), wherein nanostructure-film(s) may form at least semi-transparent anode(s) and/or cathode(s) through use of buffer layer(s).

The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.

The invention relates to a TFT-LCD pixel structure, a manufacturing method and a broken wire repairing method. The TFT-LCD pixel structure comprises a plurality of pixel cells limited by a grid wire and a data wire, wherein a thin-film transistor and a pixel electrode are formed in each pixel cell, a first public electrode wire is formed on the lower side of the grid wire, a second public electrode wire is formed on the upper side of the grid wire, a first light blocking strip is formed on the left side of the pixel cell, and a second light blocking strip is formed on the right side of the pixel cell; the first public electrode wire, the second public electrode wire, the first light blocking strip and the second light blocking strip form an integrated structure and form an annular structure on the periphery of the pixel cell; and the second public electrode wire positioned on the upper side of the grid wire is connected with the first public electrode positioned on the lower side of the grid wire through a connecting electrode. The TFT-LCD pixel structure can be repaired quickly and efficiently, and has high success rate.

A proximity-based mutually capacitance-sensitive touchpad that is disposed directly beneath a keypad keymat of a mobile telephone, wherein posts associated with each key pass through a mutually capacitance-sensitive sensor electrode grid of the touchpad such that the keypad posts do not interfere with touchpad detection and tracking of a pointing object that moves along the keypad surface, to thereby enable touchpad data entry, cursor control, and scroll bar control on a display of the mobile telephone, wherein the keypad posts actuate mechanical switches underneath the touchpad.

The invention discloses a process for manufacturing a solar cell by twice screen printing and grooving, which is used for manufacturing the solar cell by twice electrode printing and comprises a grooving process and a twice printing process, wherein the grooving process comprises the step of performing grooving on an electrode grid line area on the surface of a silicon wafer so as to form an etched groove in the electrode grid line area; and the twice printing process comprises the following steps of: a, primary electrode printing, namely, filling printing electrode paste into the etched groove and performing drying to form a first layer of electrode in the etched groove; and b, secondary electrode printing, namely, printing the electrode on the outer surface of the first layer of electrode so as to form a second layer of electrode in the electrode grid line area on the surface of the silicon wafer. The solar cell manufactured by the method has relatively lower series resistance, a selective emitter and relatively higher conversion efficiency, and can reduce shading loss; and the electrode paste is difficult to spread in a sintering process.

A capacitance sensitive proximity and touch-sensitive detection device having an XY electrode grid sensor, wherein a compensation matrix is created when the capacitance sensitive touchpad is installed within a PIN Entry Device (PED), wherein the compensation matrix enables the capacitance sensitive touchpad to compensate and be balanced for the operating environment of the PED, and wherein physical keys of a keypad can be also be individually identified as an actuated key by using a unique “key profile” for each key, and wherein the insertion of a foreign conductive and/or dielectric material such as an intruding sensor in proximity of the XY electrode grid sensor of the touchpad will cause an imbalance in the electrodes on the capacitance sensitive proximity and touch-sensitive detection device, thereby alerting detection circuitry that tampering has occurred with the PED.

An organic light emitting display device includes a light shield layer formed on a substrate and a buffer layer formed on an entire surface of the substrate, an oxide semiconductor layer and first electrode formed on the buffer layer, a gate insulation film and gate electrode formed on the oxide semiconductor layer while being deposited to expose both edges of the oxide semiconductor layer, an interlayer insulation film formed to expose both the exposed edges of the oxide semiconductor layer and the first electrode, source and drain electrodes connected with one edge and the other edge of the oxide semiconductor layer, respectively, and a protective film formed to cover the source and drain electrodes while exposing a region of the first electrode so as to define a luminescent region and a non-luminescent region.

A method and neurostimulation control system for programming electrodes disposed adjacent tissue of a patient. A fixed spatial grid of electrode positions is generated. One of the electrodes is designated as a reference electrode to be currently examined, and assigned to one of the electrode grid positions. One or more previously unassigned ones of the electrodes neighboring the reference electrode are assigned respectively to one or more of the electrode grid positions immediately surrounding the electrode grid position to which the reference electrode is assigned. The electrodes are programmed based on the assignment of the electrodes to the electrode grid positions.

There is provided a thin-film transistor forming substrate in which at least one of a source electrode, a drain electrode, and a gate electrode, which are constituent elements of a thin film transistor, or a first electrode is included on a face of a substrate main body that is located on any one side in a thickness direction. An embedded wiring that is connected to one of the source electrode, the drain electrode, the gate electrode, and the first electrode is buried inside the substrate main body.

A TFT array substrate and a manufacturing method thereof, where the TFT array substrate includes a substrate; a gate line and a gate electrode integrated therewith, which are covered by a gate insulating layer, a semiconductor layer, and a ohmic contact layer sequentially. An insulating layer is formed on the resulting substrate and on both sides of the gate line and the gate electrode, the gate insulating layer, the semiconductor layer, and the ohmic contact layer. A trench is then formed in the ohmic contact layer to divide the ohmic contact layer over the semiconductor layer. A data line and first and second source/drain electrodes are then formed on the insulating layer and the ohmic contact layer.

There are provided an oxide TFT, a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the display device. The oxide thin film transistor includes: a gate electrode formed on a substrate; a gate insulating layer formed on the entire surface of the substrate including the gate electrode; an active layer pattern formed on the gate insulating layer above the gate electrode and completely overlapping the gate electrode; an etch stop layer pattern formed on the active layer pattern and the gate insulating layer; and a source electrode and a drain electrode formed on the gate insulating layer including the etch stop layer pattern and the active layer pattern and spaced apart from one another, and overlapping both sides of the etch stop layer pattern and the underlying active layer pattern.

A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.

A system and method for providing security for a point-of-sale (POS) terminal or an encrypting PIN pad (EPP) by protecting the signals that could be directly probed on a touch sensor electrode grid or remotely probed such as through power supply signals or RF emissions, wherein the drive signals are randomly applied to drive electrodes in order to prevent tracking of drive signals, and charge is injected on sense lines to hide PIN data.

The invention discloses a low-cost efficient solar cell electrode grid line structure which comprises two parts of main grid lines and thin grid lines, wherein the main grid lines are symmetrically distributed by taking a silicon wafer center as a center, the thin grid lines are equidistantly distributed in the way of being vertical to the main grid lines in parallel, the main grid lines adopt a sectional type design, and all the subsections are connected by thin lines. The electrode grid line structure adopts a design that the grid lines are thinned, the shading areas of the grid lines are reduced, the number of the grid lines is increased so that the lateral transmission loss of a carrier is lowered and the collection efficiency of the carrier is increased; moreover, the main grid lines are divided into sections, thinned and hollowed out additionally, so the silver usage is reduced, the manufacturing cost of a solar cell is reduced, meanwhile, the contact area compound is lowered, accordingly, the open-circuit voltage of the solar cell is increased, and the cost is greatly lowered; and compared with the widespread products of the industry, in the design scheme which is obtained by optimizing the scheme, the shading area of the grid lines on the front side of the solar cell is reduced by about 1%, the conversion efficiency is improved by 0.2-0.3%, and the silver paste consumption is reduced by about 35%.

Disclosed is a thin film transistor including a gate electrode on a substrate. A gate dielectric layer is disposed on the gate electrode and the substrate, and source/drain electrodes are disposed on the gate dielectric layer overlying two edge parts of the gate electrode. A channel layer is disposed on the gate dielectric layer overlying a center part of the gate electrode, and the channel region contacts the source/drain electrodes. An insulating capping layer overlies the channel layer, wherein the channel layer includes an oxide semiconductor.

The invention discloses a method for preparing a positive plate of a lead storage battery, and belongs to the technical field of preparation of electrode materials, in particular to a process for a preparation method for the lead storage battery. In the method, a lead alloy is used as a raw material, a lead-alloy positive electrode grid formed by fusion and casting is used as the positive electrode and is subjected to surface modification in rare earth sulfate and sulphuric acid solution by an anodic electrochemical oxidation process to prepare a positive plate of the lead storage battery that the surface of the lead alloy is modified by the rare earth; and lead powder, water, sulfuric acid and rare earth oxides or rare earth sulfate and additives are mixed into a lead plaster, and the lead plaster is subjected to plate coating, solidification, drying and formation to prepare the rear-earth modified positive electrode grid of the lead storage battery. The method is simple, reduces the using amount of the rear earth and improves the utilization ratio of the rear earth, avoids the difficulty in preparing the positive electrode grid from the lead-rare earth alloy, is easy to uniformly and quantitatively dope trace rare-earth elements on the surface of the electrode, and realizes the control of the surface performance of the electrode.