284 results about "Electrode Grid" patented technology

The present disclosure relates to the technical field of display chips. Disclosed are a full-color MicroLED and a manufacturing method therefor. The full-color MicroLED comprises a driving substrate, a first light-emitting layer, a first connecting layer, a second light-emitting layer, and a second connecting layer; the driving substrate comprises a first P-type semiconductor electrode transition layer; the first light-emitting layer comprises first light-emitting units and a second P-type semiconductor electrode transition layer; the first connecting layer comprises a first N-type semiconductor electrode transition layer, first N-electrode grids, and a third P-type semiconductor electrode transition layer; the second light-emitting layer comprises second light-emitting units and a fourth P-type semiconductor electrode transition layer; the second connecting layer comprises a second N-type semiconductor electrode transition layer and second N-electrode grids; a color conversion layer is provided at the position of the second connecting layer corresponding to some of the second light-emitting units. In the present disclosure, the driving substrate drives the light-emitting units on the first light-emitting layer and the second light-emitting layer to respectively emit green light and blue light, and then part of the blue light of the second light-emitting units is converted into red light by means of the color conversion layer, thereby achieving full-color light emission.

The invention discloses a battery microstructure three-dimensional reconstruction simulation method and system based on an electrochemical model and computer equipment. The method comprises the following steps: acquiring a lithium ion battery electrode scanning sequence image, and acquiring a three-dimensional voxel model and an electrode grid chart; s2, acquiring key microstructure parameters of the electrode; s3, performing mesh generation on three-phase voxels in the electrode mesh chart to obtain a mesh file for finite element calculation; and S4, comparing the experimental data of the battery with the simulation data of the three-dimensional microstructure electrochemical model, adjusting the precision of the three-dimensional microstructure electrochemical model, and optimizing related parameters. According to the invention, three-phase accurate segmentation is carried out by using filtering and denoising, image enhancement and connectivity and a watershed segmentation algorithm, and a three-dimensional voxel model containing real particle morphology, cracks and pores and an electrode grid chart are reconstructed; the problems that in the prior art, a lithium ion battery microstructure simulation model is large in idealization deviation and inconsistent with a real structure, and consequently performance prediction is inaccurate are solved.

The present disclosure provides a solar cell, a module and a system. The solar cell comprises a silicon substrate, first doped layers, second doped layers, positive electrode grid lines, negative electrode grid lines and a first PAD portion. The second doped layers are in recombination contact with the first doped layers at predetermined positions, so as to form leakage recombination contact structures. A first PAD point and a second PAD point of the first PAD portion are electrically and respectively connected to at least one positive electrode grid line and at least one negative electrode grid line.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention provides an electrode grid line and a preparation method thereof and conductive slurry, the electrode grid line comprises a seed layer and a base metal layer superposed on the upper layer of the seed layer, the base metal proportion in the conductive phase of the base metal layer is greater than 68%, the seed layer comprises a main grid and a seed layer fine grid, the base metal layer comprises base metal layer fine grids electrically connected with the seed layer fine grids in a one-to-one correspondence mode, at least one of the seed layer fine grids and the base metal layer fine grids is further provided with a plurality of contact pins, and the contact pins are distributed in the length direction of the corresponding fine grids at intervals. And the width of the contact pin in the line width direction of the fine grid is greater than the line width of the fine grid. The electrode grid line with the preset height is formed in a grid stacking mode, base metal is utilized by the base metal layer, the overall silver consumption amount of the electrode grid line is effectively reduced, the part, exceeding the width of the thin grid line where the contact pin is located, of the contact pin arranged on the thin grid line can be used for compensating printing precision deviation, the precision requirement for printing operation is reduced, and the contact performance is improved.

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

The present application relates to the technical field of leakage detection, in particular to a method and system for detecting leakage of an anti-seepage layer in the construction of an artificial wetland, which determines the seepage time period in which each electrode grid may produce seepage by analyzing the changes in the potential difference data and humidity data of the electrode grid below the anti-seepage layer; based on the seepage time period, analyzes the coincidence of liquid diffusion between different electrode grids, and divides the electrode grid into several diffusion regions; divides the diffusion regions into suspected damage regions and diffusion interaction regions, and analyzes the area relationship between the suspected damage regions and the diffusion interaction regions to obtain the seepage damage probability of the diffusion region corresponding to each electrode grid; and according to the seepage damage probability, marks the leakage point region. Through the present application, the region where the anti-seepage layer may be damaged and diffused can be more accurately positioned, the accuracy of identifying the specific position of the anti-seepage layer where leakage occurs is improved, and the credibility of the leakage detection result of the anti-seepage layer is further improved.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first passivation layer, a second passivation layer and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode, the drain electrode, and the gate structure are disposed above the second nitride-based semiconductor layer. The first passivation layer is disposed above the second nitride-based semiconductor layer and covers the gate structure. The second passivation layer is disposed above the first passivation layer and in a region between the source and drain electrodes. The field plate is disposed above the second passivation layer and in the region between the source electrode and drain electrode, in which the field plate contacts at least one enclosed air gap above the first passivation layer.

This invention discloses a tunable broadband photodetector based on a Schottky junction, comprising: an N-type silicon substrate, a gate ferroelectric dielectric, a gate electrode, a source electrode, and a drain electrode; the source electrode, gate ferroelectric dielectric, and drain electrode are sequentially disposed on the N-type silicon substrate, and the gate electrode is disposed on the gate ferroelectric dielectric; the gate ferroelectric dielectric is made of hafnium oxide, a ferroelectric material, and the gate ferroelectric dielectric and the gate electrode together constitute a ferroelectric gate; the gate electrode is made of a transparent metal oxide. This invention utilizes silicon CMOS manufacturing technology and a simple device structure, greatly reducing the fabrication difficulty of silicon-based infrared detectors, and by leveraging the characteristic that the polarization intensity of ferroelectrics weakens under infrared light, extends the detection long-wavelength limit of silicon-based infrared detectors to the near-infrared band. This invention also discloses a method for fabricating and applying a tunable broadband photodetector based on a Schottky junction.

The present application relates to a semiconductor device and a semiconductor memory device. The semiconductor device of an embodiment includes an oxide semiconductor layer; a gate electrode; a gate insulating layer; a first electrode and a second electrode electrically connected to the oxide semiconductor layer; a first conductive layer provided at at least one of a position between the oxide semiconductor layer and the first electrode and a position between the oxide semiconductor layer and the second electrode, containing at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and including a first portion and a second portion, the first portion having a higher atomic concentration of the metal element than an atomic concentration of aluminum in the first portion, and the second portion having a higher atomic concentration of aluminum than an atomic concentration of the metal element in the second portion; and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer.

The invention discloses a solar photovoltaic anti-skid floor tile which comprises a plurality of anti-skid photovoltaic power generation floor tiles with different areas and the same structure, a mounting guide rail used for assembling and combining the multiple anti-skid photovoltaic power generation floor tiles and LED lamp strips assembled between gaps of the anti-skid photovoltaic power generation floor tiles. Through the micro-bump anti-skid structure on the surface of the tempered glass panel, the wet friction coefficient is increased while the low dust adhesion characteristic of a smooth surface is kept, and the anti-skid requirement is met. By adopting the back wiring battery technology, the electrode grid lines are hidden on the back surface of the battery piece, so that the surface of the floor tile presents a pure black grain-free integrated visual effect, and the anti-shielding performance is excellent. The bottom supporting plate adopts a lightweight composite material or aluminum alloy combined with a honeycomb mould pressing SMC forming process, the weight of a single floor tile is greatly reduced compared with that of a traditional scheme, and in cooperation with the design of heat dissipation holes of an inner cavity of a honeycomb structure, the floor tile has the strict requirements for high-strength bearing force and supporting of various environments, the service life is further prolonged, and the floor tile is suitable for popularization and application. And the materials can be completely recycled.

The embodiment of the present application provides a kind of N-type IBC battery negative electrode grid silver paste, N-type IIBC battery and preparation method thereof, wherein, the N-type IBC battery negative electrode grid silver paste provided in the embodiment of the present application includes organic auxiliary agent, silver powder, organic binder and doped glass powder, and the doping element of the doped glass powder is antimony, tellurium and tungsten.By doping antimony, tellurium and tungsten elements in glass powder, antimony element is the same as phosphorus, and the doping of N area can be increased;And tellurium and tungsten have the effect of dissolving silver, which can reduce the contact resistivity of silver grid line, improve the fill factor, thereby improving the photoelectric conversion efficiency of battery;Thus, the problem that the existing N-type IBC battery cannot form n+ region, so that the photoelectric conversion efficiency of N-type IBC battery is not good.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

An example semiconductor device includes a gate stack structure, a channel structure, and multiple gate contacts. The gate stack structure includes multiple interlayer insulating layers and multiple gate electrodes stacked alternately on top of each other. The channel structure extends through the gate stack structure. Each gate contact extends through a portion of the gate stack structure to be electrically connected to a gate electrode. The gate stack structure includes a first stack portion and a second stack portion on the first stack portion, the first stack portion including at least one gate stack portion. The multiple gate contacts include multiple first contacts and multiple second contacts. The multiple first contacts are electrically connected to multiple first electrodes, respectively. The multiple second contacts are electrically connected to multiple second electrodes, respectively.

The invention relates to a nerve interface device based on a transparent organic thin film transistor and a manufacturing method thereof. The device comprises a substrate, a first electrode layer comprising a plurality of source electrodes, a plurality of drain electrodes and a plurality of first electrodes, an organic semiconductor layer, a first insulating layer, a second electrode layer comprising a plurality of gate electrodes and a plurality of second electrodes, an interconnection wire layer, a biological electrode layer and a packaging layer which are sequentially arranged from bottom to top, a plurality of neural interface units are arranged in the device, each neural interface unit comprises a plurality of transistors, at least one capacitor and two biological electrodes, each transistor comprises a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer and a first insulating layer between the transistor electrodes, two polar plates of each capacitor are respectively a first electrode and a second electrode which are opposite in position; the material of each layer of the device is a transparent flexible material. The device is low in cost, large in area, high in channel number, long in service life, and high in time and spatial resolution.

A semiconductor device includes: a substrate; a first active pattern and a second active pattern, the first active pattern and the second active pattern being spaced apart, a second width of the second active pattern being greater than a first width of the first active pattern; a first plurality of nanosheets stacked on the first active pattern and spaced apart from each other; a second plurality of nanosheets stacked on the second active pattern and spaced apart from each other, the second plurality of nanosheets having a second width greater than the first width of the first plurality of nanosheets; a gate electrode surrounding the first plurality of nanosheets and the second plurality of nanosheets; first internal spacers located on both sidewalls of the gate electrode between adjacent first plurality of nanosheets; and a second internal spacer on both sidewalls of the gate electrode between adjacent second plurality of nanosheets, the second internal spacer having a thickness less than a thickness of the first internal spacer.

A semiconductor device includes a plurality of trenches penetrating through a source region and a base region, and a mesa region as a region between two of the plurality of trenches. A gate electrode that faces the base region with a gate insulating film interposed between the gate electrode and the base region is formed in each trench. An electric field relieving layer is provided immediately below each trench. A super junction structure in which a first pillar layer and a second pillar layer are alternately arranged is formed between the base region and the drift layer. A width of the first pillar layer is equal to or less than a width of the electric field relieving layer.

The invention relates to a C-type contact structure of a two-dimensional device and a preparation method and application of the C-type contact structure. The C-type contact structure comprises a substrate (1), a gate electrode (2), a gate dielectric layer (3), a first-layer source-drain electrode (4), a two-dimensional semiconductor channel (5) and a second-layer source-drain electrode (6) which are sequentially arranged from bottom to top. And the second layer of source and drain electrode (6) and the first layer of source and drain electrode (4) are contacted and connected at the two sides of the two-dimensional semiconductor channel (5) to form C-type contact, and the two sides of the two-dimensional semiconductor channel (5) are wrapped between the second layer of source and drain electrode (6) and the first layer of source and drain electrode (4). Compared with the prior art, an upper layer of contact metal and a lower layer of contact metal (the first layer of source-drain electrode and the second layer of source-drain electrode) are designed on the contact between a channel (a two-dimensional semiconductor channel) and the source and the drain to form a C-type metal-semiconductor contact structure, so that the contact area of the two is effectively increased, and the contact resistance is reduced.

The embodiment of the present application provides an IBC battery aluminum paste and an IBC battery, wherein the IBC battery aluminum paste provided by the embodiment of the present application comprises an organic additive, boron powder, aluminum powder, gallium powder, glass powder and an organic binder. By adding gallium powder in the aluminum paste, because the gallium element has etching effect and high density, it is faster than aluminum to drop to the silicon surface in the sintering process, so that the Ga-Si contact probability is increased, the contact resistance of the paste and the battery is reduced, and a high open circuit voltage can be maintained. At the same time, because part of the aluminum powder is replaced by gallium, the content of aluminum is reduced, which is beneficial to reducing the side effect of Al, so that the Al-Si reaction is weakened, the formed aluminum silicon corrosion pit is shallow, the recombination is reduced, so as to improve the open circuit voltage and the photoelectric conversion efficiency of the battery. Therefore, the problem that the existing IBC battery aluminum paste is easy to form metal recombination in the cooling process after being sintered into a positive electrode grid line, resulting in the decrease of the open circuit voltage and the photoelectric conversion efficiency of the battery piece is solved.

Systems, methods, and devices disclosed herein include a transcutaneous spinal cord stimulation (tSCS) system with a stimulation electrode grid. The stimulation electrode grid includes a plurality of anodes and a plurality of cathodes, and the stimulation electrode grid is operable for placement proximate to a spinous process. The system also includes a particularized electrical field generated by selective activation of the stimulation electrode grid. Moreover, a localized tSCS, provided by the particularized electrical field is operable to cause a neuromodulation effect. Also, the stimulation electrode grid includes a substrate material. The plurality of cathodes and the plurality of anodes are both arranged as rows or columns on the substrate material to form an integrated unit. The stimulation electrode grid includes a plurality of selectively activated electrode array activation configurations, and the neuromodulation effect generated by the system can be used to enhance voluntary extremity function and pain management.

The present invention relates to a spin current generation device using an SiOC topological insulator, and a manufacturing method therefor. The spin current generation device using an SiOC topological insulator, according to the present invention, comprises: a substrate (200); a gate electrode (303) disposed on the substrate (200); a gate insulating film (100) disposed on the substrate (200) and the gate electrode (303); a source electrode (301) disposed on the gate insulating film (100); and a drain electrode (302) disposed on the gate insulating film (100), wherein the gate insulating film (100) is composed of an SiC topological insulator and has a dielectric constant of 0.01 to 2.5.

The invention discloses a display panel. The display panel comprises a substrate and a sub-pixel, the sub-pixel is arranged on the substrate and comprises a transistor, and the transistor comprises a grid electrode, a semiconductor layer, a drain electrode, a source electrode and a dummy electrode. The grid electrode is arranged on the substrate, the semiconductor layer is arranged on the grid electrode, and the semiconductor layer comprises a first part and a second part which are separated. The drain electrode is arranged on the first part of the semiconductor layer and is electrically connected with the first part. The source electrode is arranged on the second part of the semiconductor layer and is electrically connected with the second part. The dummy electrode is disposed on the substrate, wherein the dummy electrode partially overlaps the first portion and the second portion of the semiconductor layer, respectively. The dummy electrode is arranged between the source electrode and the drain electrode and is separated from the source electrode and the drain electrode, and the dummy electrode is electrically connected in a floating mode.

This application relates to a semiconductor device in the semiconductor field, comprising a substrate; source / drain regions located above the substrate, and a first oxide semiconductor located between the source / drain regions, wherein the source / drain regions only contact a portion of the side surface of the first oxide semiconductor, wherein the thickness of the first oxide semiconductor is greater than the thickness of the source / drain regions, and wherein the channel length between the source / drain regions is less than 5 μm; a gate dielectric located above the first oxide semiconductor; a gate electrode located above the gate dielectric; a passivation layer located above the substrate, source / drain regions, and gate electrode, and surrounding the gate electrode, the gate dielectric, and a portion of the side surface of the first oxide semiconductor; a source electrode and a drain electrode contacting the source / drain regions respectively through openings; wherein the source / drain regions comprise the same material as the first oxide semiconductor, but after processing, the carrier concentration is much higher than the carrier concentration in the first oxide semiconductor. This application also includes a semiconductor device fabrication method and an electronic device.

A semiconductor device, a manufacturing method therefor, and an electronic apparatus are disclosed. The semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; a word line, penetrating the different layers and extending in the direction perpendicular to the substrate; the transistor includes a first electrode, a gate insulating layer, a semiconductor layer surrounding side walls of the word line, and a protective layer disposed between the semiconductor layer and side walls of the gate insulating layer; the first electrode is provided in a first groove of the semiconductor layer.

This drive circuit for a power conversion device is characterized in that a gate driver (25) that drives a collector gate (CG) of a CG-IGBT (28), which is an upper arm output element, has: a charge storage circuit (33) that is provided with a capacitor (35) and a backflow prevention element (34); and a charge / discharge control circuit (32) provided with a switching element (36) and a resistor (37), one terminal of the capacitor (35) being connected to a main power source (31) of the power conversion device via the backflow prevention element (34) and connected to a collector gate (CG) of the CG-IGBT (28), and the other terminal of the capacitor (35) being connected to a reference potential of the power conversion device via the switching element (36) and connected to a collector gate (CG) of the CG-IGBT (28) via the backflow prevention element (34). And is connected to a main power source (31) of the power conversion device via a resistor (37).

The application relates to an N-type finger-shaped polycrystalline silicon passivation structure and a preparation method thereof. The structure comprises non-contact areas and contact areas staggered along the length direction of a silicon wafer substrate, and a side wall between the non-contact areas and the contact areas; the contact area comprises, from the side close to the silicon wafer substrate to the side away from the silicon wafer substrate, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer and an electrode grid line; the thickness of the tunneling oxide layer is 1-5 nm, and the thickness of the phosphorus-doped polycrystalline silicon layer is 50-200 nm; the non-contact areas, the contact areas and the side wall are all deposited with an aluminum oxide / silicon nitride stack; the aluminum oxide / silicon nitride stack of the contact area is located on the outside of the phosphorus-doped polycrystalline silicon layer, and the aluminum oxide / silicon nitride stack of the non-contact area is located on the silicon wafer substrate; the side wall is gradually inclined upward from the non-contact area to the contact area, and the inclination angle alpha of the side wall is 40-90 degrees. The application has the effects of good passivation effect and low production cost.

This silicon carbide semiconductor device is provided with a silicon carbide substrate having a first main surface and a second main surface. The silicon carbide substrate has: a drift region of a first conductivity type; a body region of the second conductivity type on the drift region; a source region of the first conductivity type on the body region; a connection region of a second conductivity type provided in contact with the lower portion of the body region; and an electric field relaxation region of a second conductivity type provided in contact with the underside of the connection region and provided with a gate trench having a side surface extending from the first main surface to the drift region and a bottom surface connected to the side surface, the silicon carbide semiconductor device having: a gate insulating film in contact with the gate trench; and a gate electrode on the gate insulating film, the gate trench extending along a first axis, the connection region being farther from the gate trench than the body region along a second axis perpendicular to the first axis, the electric field mitigation region being farther from the gate trench along the second axis than the connection region, a first thickness of the electric field mitigation region being greater than a second thickness of the connection region.

Provided is a semiconductor device occupying a small area. Semiconductor fabrication includes a vertical transistor, a TGSA-type transistor, a first insulating layer, and a second insulating layer. Each of the two transistors includes two gate electrodes (a gate electrode and a back gate electrode) provided so as to sandwich the semiconductor layer. The first insulating layer is between one of the source electrode and the drain electrode of the vertical transistor and the back gate electrode, and the second insulating layer is between the back gate electrode of the vertical transistor and the other of the source electrode and the drain electrode. A back gate insulating layer, a semiconductor layer, a gate insulating layer, and a gate electrode of the vertical transistor are provided in this order along a sidewall of an opening provided in the other of the first insulating layer, the back gate electrode, the second insulating layer, and the source electrode and the drain electrode. The TGSA type transistor is disposed on the second insulating layer. The back gate insulating layers of the two transistors have a function of supplying oxygen to the semiconductor layer.

The provided is a preparation method of electrode grid lines, and a photovoltaic (PV) cell. The preparation method of electrode grid lines includes the following steps: S1: providing a polymer layer as a transfer substrate; S2: applying conductive paste onto a formed side of the polymer layer to at least completely fill a trench in the formed side, and removing excess conductive paste from a surface of the polymer layer; S3: providing a base material, aligning and bonding the side of the polymer layer applied with the conductive paste to the base material, and transferring the conductive paste onto the base material through a transfer method with a preset process parameter; S4: removing the polymer layer; and S5: sintering the conductive paste onto the base material, and forming electrode grid lines with a preset aspect ratio.

The utility model relates to the technical field of battery part manufacturing equipment, and provides a battery grid casting device and a release agent spraying module thereof, and the release agent spraying module comprises a first supporting column, a first mounting arm and a spraying assembly; the battery grid casting device comprises a rack, a second supporting column, a second mounting arm, a movable mold and a fixed mold; and the spraying assembly can spray a release agent to the fixed mold and the movable mold. The release agent spraying module is designed for a traditional battery grid casting device, the production efficiency and the spraying quality can be improved, and therefore battery grids with better quality can be produced. According to the battery grid casting device, the release agent spraying module is additionally arranged, so that the production efficiency is improved, and the quality of finished products is improved.