593 results about "Electrode Grid" patented technology

The utility model discloses a solar cell and a photovoltaic assembly, the surface of a substrate of the solar cell is provided with a plurality of grid line electrodes, each grid line electrode comprises a plurality of fine grid lines arranged at intervals along a first direction, and the polarities of two adjacent fine grid lines are opposite; the fine grid lines are provided with conductive connecting parts; along the first direction, the plurality of conductive connection parts of the plurality of fine grid lines with the same polarity form conductive connection groups, and the plurality of columns of conductive connection groups are arranged at intervals along the second direction; the solar cell further comprises a plurality of insulating pieces covering the area where the conductive connecting sets are located, and gaps exist between the insulating pieces and the conductive connecting parts. In the thickness direction of the substrate, the thickness of the insulating part is smaller than that of the conductive connecting part. The thickness of the insulating part is lower than that of the conductive connecting part, so that the possibility that the welding strip is influenced by the insulating part when being connected with the conductive connecting part is reduced, and the overall working efficiency of the solar cell is improved.

The invention relates to a solar cell and a preparation method and application thereof.The solar cell comprises a silicon substrate, the silicon substrate is provided with a light receiving face and a backlight face which are arranged back to back, the surface of the backlight face comprises a laminated structure and a negative electrode grid line arranged on the surface of the laminated structure, the backlight face comprises at least one groove, and the negative electrode grid line is arranged in the groove. A groove is formed in the light receiving surface, the negative grid line is arranged in the groove, a first suede surface is formed on the inner wall of the groove, a second suede surface is formed on the light receiving surface, and the density of the first suede surface is smaller than that of the second suede surface in unit area. The solar cell provided by the invention not only can realize efficiency maximization, but also has excellent reliability.

A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

The present disclosure relates to the technical field of display chips. Disclosed are a full-color MicroLED and a manufacturing method therefor. The full-color MicroLED comprises a driving substrate, a first light-emitting layer, a first connecting layer, a second light-emitting layer, and a second connecting layer; the driving substrate comprises a first P-type semiconductor electrode transition layer; the first light-emitting layer comprises first light-emitting units and a second P-type semiconductor electrode transition layer; the first connecting layer comprises a first N-type semiconductor electrode transition layer, first N-electrode grids, and a third P-type semiconductor electrode transition layer; the second light-emitting layer comprises second light-emitting units and a fourth P-type semiconductor electrode transition layer; the second connecting layer comprises a second N-type semiconductor electrode transition layer and second N-electrode grids; a color conversion layer is provided at the position of the second connecting layer corresponding to some of the second light-emitting units. In the present disclosure, the driving substrate drives the light-emitting units on the first light-emitting layer and the second light-emitting layer to respectively emit green light and blue light, and then part of the blue light of the second light-emitting units is converted into red light by means of the color conversion layer, thereby achieving full-color light emission.

A photovoltaic module with a hidden bus bar is provided and comprises battery strings, the battery strings are a plurality of battery pieces connected in series in the X direction, and the plurality of battery strings are arranged in the Y direction; the battery pieces comprise positive electrode grid lines and negative electrode grid lines which are alternately arranged and are connected through positive electrode welding strips and negative electrode welding strips, and the battery pieces in the battery strings are connected through the positive electrode welding strips or the negative electrode welding strips; the bus bars are arranged along the Y direction and are connected with two adjacent battery strings; the bus bar comprises a bus bar main body and a plurality of extension parts which are arranged at intervals along the extension direction of the bus bar main body and are perpendicular to the main body, the extension parts are positioned on one side or two sides of the bus bar main body, and one ends of the extension parts extend out of the bus bar main body and are arranged above the first welding strip to be welded with the first welding strip; the insulating layer is arranged below the bus bar and is arranged on the second welding strip below the bus bar; wherein the first welding strip is a welding strip which is directly connected and welded with the bus bar, and the second welding strip is a welding strip which is not directly connected and welded with the bus bar. The photovoltaic module provided by the utility model does not have a sealing-off problem.

The invention belongs to the technical field of power semiconductors, and discloses a substrate voltage regulation GaN HEMT power device which comprises a P substrate, a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, a passivation layer and a floating field plate structure which are sequentially stacked from bottom to top in the vertical direction of the device. A source electrode, a gate structure and a drain electrode which are not in contact with one another are sequentially arranged on the surface of the AlGaN barrier layer in the transverse direction of the device; the floating field plate structure comprises a plurality of floating field plates which are not in contact with one another, the P substrate is connected with any one field plate in the floating field plate structure through metal, so that the potential of the P substrate is the same, the voltage of the floating field plate can regulate and control the voltage of the substrate, high voltage resistance is realized, and dynamic resistance degradation is inhibited. The method has the advantages that under the condition that on resistance is not increased, high voltage resistance is achieved, collapse of a dynamic resistor is restrained, additional process steps are not increased, the area of a chip is not increased additionally, and cost is saved.

A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.

The invention discloses a crystalline silicon cell module, a preparation method and a photovoltaic system, and belongs to the technical field of solar cells. The crystalline silicon battery assembly comprises a plurality of crystalline silicon battery pieces, the plurality of crystalline silicon battery pieces comprise a first crystalline silicon battery piece and a second crystalline silicon battery piece, the light facing surface of the first crystalline silicon battery piece is provided with a first connecting piece, and the backlight surface of the second crystalline silicon battery piece is provided with a second connecting piece; the first connecting piece comprises a first electrode grid line, the first electrode grid line is electrically connected with the light-facing surface of the first crystalline silicon battery piece, the second connecting piece comprises a second electrode grid line, the second electrode grid line is electrically connected with the backlight surface of the second crystalline silicon battery piece, and the first connecting piece and the second connecting piece extend in opposite directions so as to be connected with each other; and the first electrode grid line is in contact connection with the second electrode grid line. The electrode grid lines between the two crystal silicon battery pieces are directly connected, so that no welding strip is needed for connection, the shading influence caused by the welding strip can be avoided, and the power of the module is improved.

The invention discloses a battery microstructure three-dimensional reconstruction simulation method and system based on an electrochemical model and computer equipment. The method comprises the following steps: acquiring a lithium ion battery electrode scanning sequence image, and acquiring a three-dimensional voxel model and an electrode grid chart; s2, acquiring key microstructure parameters of the electrode; s3, performing mesh generation on three-phase voxels in the electrode mesh chart to obtain a mesh file for finite element calculation; and S4, comparing the experimental data of the battery with the simulation data of the three-dimensional microstructure electrochemical model, adjusting the precision of the three-dimensional microstructure electrochemical model, and optimizing related parameters. According to the invention, three-phase accurate segmentation is carried out by using filtering and denoising, image enhancement and connectivity and a watershed segmentation algorithm, and a three-dimensional voxel model containing real particle morphology, cracks and pores and an electrode grid chart are reconstructed; the problems that in the prior art, a lithium ion battery microstructure simulation model is large in idealization deviation and inconsistent with a real structure, and consequently performance prediction is inaccurate are solved.

A semiconductor device comprising a first lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction, a first and second plurality of nanosheets stacked apart from one another in a vertical direction, a first gate electrode extending in a second horizontal direction, the first gate electrode surrounding the first plurality of nanosheets, a second gate electrode extending in the second horizontal direction, the second gate electrode surrounding the second plurality of nanosheets, a source / drain region between the first and second gate electrodes, a source / drain contact penetrating the first lower interlayer insulating layer and the insulating pattern, the source / drain contact electrically connected to the source / drain region, and a gate contact penetrating the first lower interlayer insulating layer and the insulating pattern, the gate contact electrically connected to the second gate electrode, at least a portion of a sidewall of the gate contact contacting the source / drain contact.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut is confined within the gate trench such that it does not extend beyond the walls of the gate trench as defined by gate spacer structures. Additionally, the gate dielectric does not form on any surface of the gate cut, such that the gate cut directly contacts the gate electrode.

The invention discloses a preparation method of a TBC battery electrode grid line, the electrode grid line and a TBC battery, and belongs to the technical field of solar cells, and the preparation method comprises the following steps: carrying out double-sided polishing on a silicon wafer; sequentially depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon wafer, and performing boron diffusion; digging an N region and a PN connection partition region on the back surface of the silicon wafer; sequentially depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon wafer, and performing phosphorus diffusion on the basis of the tunneling oxide layer and the intrinsic polycrystalline silicon layer; digging a P region and a GAP region on the back surface of the silicon wafer, and digging a hole channel by using a second laser; removing the borosilicate glass layer and the phosphorosilicate glass layer in the pore channel area; sequentially depositing an aluminum oxide layer and a silicon nitride layer on the surface of the silicon wafer; printing non-burn-through slurry in the main grid areas of the P area and the N area through the silk screen printing plate; and carrying out laser-assisted sintering on the auxiliary grid line pore channel region. The completeness of a passivation film layer structure on the back surface of the battery piece is ensured, meanwhile, the contact area of a metal electrode and a silicon substrate is reduced, and metal contact recombination is effectively reduced.

The present disclosure provides a solar cell, a module and a system. The solar cell comprises a silicon substrate, first doped layers, second doped layers, positive electrode grid lines, negative electrode grid lines and a first PAD portion. The second doped layers are in recombination contact with the first doped layers at predetermined positions, so as to form leakage recombination contact structures. A first PAD point and a second PAD point of the first PAD portion are electrically and respectively connected to at least one positive electrode grid line and at least one negative electrode grid line.

A highly reliable semiconductor device is provided. The semiconductor device includes first to third transistors and a capacitor. In the first transistor, one of a source and a drain is supplied with a first signal, the other of the source and the drain is connected to a gate of the second transistor and one electrode of the capacitor, and a gate is supplied with a second pulse signal. In the second transistor, one of a source and a drain is supplied with a first pulse signal, and the other of the source and the drain is connected to the other electrode of the capacitor and one of a source and a drain of the third transistor. In the third transistor, the other of the source and the drain is supplied with the first potential, and a gate is supplied with a second signal that is an inverted signal of the first signal. The first pulse signal is a clock signal, and the second pulse signal has a duty ratio of 55% or lower.

The invention relates to a composition for transfer printing, a preparation method thereof and an electrode grid line preparation method, and relates to the technical field of photovoltaic cell manufacturing, and the composition for transfer printing comprises the following components by weight: 6-40% of polyvinyl alcohol; 0.05-5% of a plasticizer; 3-20% of a coalescing agent; 0.05 to 5% of a surfactant; 1-20% of a hydrophilic material; 0.01%-0.5% of a release agent; 0.01 to 1 percent of a flatting agent; 0.01 to 1 percent of a defoaming agent; and the balance of water. Through reasonable component proportion, the defects of an existing water-soluble film are optimized, and the dissolution speed, the environmental protection property, the mechanical property and the compatibility with a silicon wafer or conductive slurry of the water-soluble film are improved; by adding the surfactant, the hydrophilic material, the plasticizer and the coalescing agent, the flexibility, the tear resistance and the water solubility of the film are improved, so that the film has better mechanical properties, the defect of the traditional PVA film in the aspect of dissolution rate is overcome, and the quick water solubility, the good mechanical properties and the environmental protection property of the film are realized; and the transfer printing effect of the thin film and the adaptability of the thin film to a silicon wafer can be improved.

An array substrate includes sub-pixels, gate lines and data lines. The sub-pixels form pixel groups each including the first and second sub-pixels. The first sub-pixel includes a first transistor and a first electrode group including a first pixel electrode and a first commons electrode. The second sub-pixel includes a second transistor and a second electrode group including a second pixel electrode and a second common electrode. The gate lines form gate line groups each including a first gate line and a second gate line. At least part of the data lines each include: first data segments between a i-th column of sub-pixels and a (i+1)th column of sub-pixels, second data segments between a (i−j)-th column of sub-pixels and a (i−j-1)-th column of sub-pixels, and third segments. An overlapping are of the first pixel electrode and first common electrode equals that of the second pixel electrode and second common electrode.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention relates to a solar cell and a preparation method thereof, and a photovoltaic module, and the solar cell comprises a substrate which is provided with a first surface and a second surface, and the first surface and the second surface are opposite to each other; the first surface is provided with a groove; the first tunneling oxide layer is arranged in the groove of the first surface; the first doped polycrystalline silicon layer is arranged on one side, far away from the first surface, of the first tunneling oxide layer in the groove; the doping type of the first doped polycrystalline silicon layer is the same as that of the substrate; the first passivation anti-reflection layer is arranged on one side, far away from the first doped polycrystalline silicon layer, of the first surface; the first electrode grid line is arranged in the groove of the first surface, and the first electrode grid line penetrates through the first passivation anti-reflection layer to be in contact with the first doped polycrystalline silicon layer; the solar cell is capable of parasitic absorption; transmission channels of carriers are increased; and the ohmic contact between the electrode grid line and the doped polycrystalline silicon layer can be enhanced.

The invention belongs to the technical field of lead ion detection, and particularly relates to a black phosphorus field-effect tube lead ion detector and a use method thereof. The detector comprises an insulating substrate, a gate electrode layer, a gate electrode insulating layer, a sensitive layer, a source electrode and a drain electrode. The gate electrode layer is arranged on the insulating substrate, and the sensitive layer is arranged on the gate electrode insulating layer; particularly, the sensitive layer comprises a black phosphorus material, and noble metal particles are arranged on the surface of the sensitive layer. According to the invention, black phosphorus is used as a sensitive material of the field effect transistor, the black phosphorus and lead ions have good chemical matching property, and a stable coordination effect is formed through surface phosphorus atoms and lead ions, so that the conductivity of a channel is obviously changed; in addition, precious metal particles are introduced to the surface of the black phosphorus sensitive layer, so that the selective adsorption capacity of lead ions is enhanced. In a word, high-selectivity and high-sensitivity electrical detection of lead ions can be realized, and a high-performance field-effect tube sensor platform is provided for rapid monitoring of heavy metal pollutants.

The invention relates to the technical field of screen printing plates, in particular to a surface coating structure and process for prolonging the service life of a screen printing plate, and the surface coating structure comprises a screen frame, a metal net is arranged in the screen frame, a pattern area right opposite to a battery piece is arranged on the metal net, and a plurality of pattern openings used for printing electrode grid lines on the battery piece are formed in the pattern area. The pattern area comprises a long edge and a wide edge, the direction of the long edge of the pattern area is parallel to the moving direction of the scraper, the metal net comprises a P surface facing the battery piece and an S surface opposite to the battery piece, the P surface is covered with a printing PI film, the S surface is covered with a reinforcing PI film, and the reinforcing PI film is provided with a notch structure used for exposing a pattern opening. And a layer of reinforced PI film is additionally arranged on the S surface to wrap and protect the metal net, and when the metal net is extruded by the scraper, the reinforced PI film can share most pressure, so that the metal net is protected, and the overall service life is prolonged. And the gap structure ensures that the silver paste can normally penetrate through the pattern area for silk-screen printing.

Techniques are provided herein to form an integrated circuit having a semiconductor layer separating gate structures from source or drain regions instead of dielectric spacers. A FET (field effect transistor) includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around any number of nanoribbons of semiconductor material. The nanoribbons may extend in a first direction between source and drain regions while the gate structure extends over the nanoribbons in a second direction. A semiconductor layer separates the gate structure from contacting the source or drain region between adjacent nanoribbons. The semiconductor layer extends in a third direction between the gate structure and the source or drain regions and also between the nanoribbons and the source or drain regions. The source or drain regions may be epitaxially grown on the semiconductor layer.

The invention relates to an aluminum-based lead alloy / cobalt-doped coated carbon fiber powder-alpha-PbO2 composite positive grid and a preparation method thereof, and belongs to the technical field of battery grids. The aluminum-based lead alloy / cobalt-doped coated carbon fiber powder-alpha-PbO2 composite positive plate grid sequentially comprises an aluminum alloy matrix, a zinc immersion antimony layer, a nanometer La2O3-doped nickel bottom layer, a Pb-Sn-Bi-Ag alloy middle layer and a porous cobalt-doped coated carbon fiber powder-alpha-PbO2 composite active layer from inside to outside. The catalytic activity of the electrode plate is improved by utilizing high conductivity and large bearing current intensity of aluminum, and the outer layer is doped with cobalt-coated carbon fiber powder-alpha-PbO2, so that the corrosion resistance of the positive grid can be improved, and the service life of the positive grid can be prolonged. Compared with a traditional lead alloy, the aluminum-based lead alloy composite positive plate grid has the advantages that the weight is reduced by more than 50%, the tensile strength is improved by 34%, and the conductivity is improved by more than 28%. Under the condition of 100% depth of discharge (DOD), the cycle period of a lead storage battery using the aluminum-based lead alloy anode grid is prolonged by 25%, and the long-term frequent charge and discharge requirements of a lead-acid energy storage battery can be met.

The invention discloses an HEMT device capable of regulating and controlling threshold voltage and a preparation method of the HEMT device. The HEMT device comprises a substrate, a nucleating layer, a buffer layer, a channel layer and a barrier layer which are arranged from bottom to top. A source electrode and a drain electrode are arranged at the two ends of the barrier layer respectively, and metal interconnection layers are arranged on the source electrode and the drain electrode; a SiN passivation layer is arranged on the barrier layer; a concave gate structure is arranged in the SiN passivation layer, and gate dielectric layers are arranged on the inner wall of the concave gate structure and the surface of the SiN passivation layer; a gate electrode is arranged on the gate dielectric layer; a SiNx protection layer is arranged above the gate electrode and on the surface of the gate dielectric layer, the gate dielectric layer comprises a dielectric insertion layer and a ferroelectric layer, the dielectric insertion layer is made of an AlN or Al2O3 material, and the ferroelectric layer is made of a material which has a wurtzite structure and contains a third nitride compound of transition metal. According to the invention, the nitride containing the transition metal and having the wurtzite structure as an epitaxial material is introduced as the ferroelectric layer, so that the performance and reliability of the device are improved.

The invention discloses a lead-sodium storage battery in the technical field of storage batteries, which comprises a positive plate, a negative plate and electrolyte: the positive plate comprises positive lead plaster and a positive grid, and the positive lead plaster comprises 100 parts of lead oxide powder, 6-12 parts of sulfuric acid, 5-15 parts of deionized water, 0.05-0.1 part of short fiber or conductive graphite fiber and 0.4-2 parts of mixture; the negative plate comprises negative lead paste and a negative plate grid, and the negative lead paste comprises 100 parts of lead oxide powder, 6-12 parts of sulfuric acid and 5-15 parts of deionized water; 0.05-0.1 part of short fibers or conductive graphite fibers and 1-10 parts of a mixture; and the electrolyte comprises 0.01-0.6 part of silicon dioxide, 30-50 parts of 98% anhydrous concentrated sulfuric acid, 2-7 parts of a sodium compound, 0.1-0.15 part of stannous mono-sulphate, 0.5-0.8 part of phosphoric acid, 1-2 parts of vanillin and 40-60 parts of deionized water. According to the lead-acid storage battery electrolyte, good low-temperature resistance of the lead-acid storage battery can be effectively realized, and the service life of the storage battery is prolonged.

The invention provides an electrode grid line and a preparation method thereof and conductive slurry, the electrode grid line comprises a seed layer and a base metal layer superposed on the upper layer of the seed layer, the base metal proportion in the conductive phase of the base metal layer is greater than 68%, the seed layer comprises a main grid and a seed layer fine grid, the base metal layer comprises base metal layer fine grids electrically connected with the seed layer fine grids in a one-to-one correspondence mode, at least one of the seed layer fine grids and the base metal layer fine grids is further provided with a plurality of contact pins, and the contact pins are distributed in the length direction of the corresponding fine grids at intervals. And the width of the contact pin in the line width direction of the fine grid is greater than the line width of the fine grid. The electrode grid line with the preset height is formed in a grid stacking mode, base metal is utilized by the base metal layer, the overall silver consumption amount of the electrode grid line is effectively reduced, the part, exceeding the width of the thin grid line where the contact pin is located, of the contact pin arranged on the thin grid line can be used for compensating printing precision deviation, the precision requirement for printing operation is reduced, and the contact performance is improved.

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

The invention relates to the technical field of TOPCon batteries, in particular to a TOPCon battery and a preparation method thereof. The preparation method of the TOPCon battery comprises the following steps: texturing a silicon wafer; performing boron diffusion doping on the front surface of the silicon wafer; carrying out acid washing and alkali washing polishing on the back surface of the silicon wafer; a first tunneling layer, a first doped polycrystalline silicon layer, a second tunneling layer and a second doped polycrystalline silicon layer are sequentially deposited on the back face of the silicon wafer, high-temperature annealing is conducted on the silicon wafer, and temporary protection layers are formed in an emitting electrode grid line area and a non-emitting electrode grid line area on the back face of the silicon wafer; performing film opening treatment on the temporary protection layer in a non-emitter grid line area; forming a textured structure on a non-emitter grid line area on the back surface of the silicon wafer; and pickling the silicon wafer. According to the technical scheme, the absorption of sunlight by the TOPCon cell can be improved, and the conversion efficiency of the TOPCon cell can be improved.

The present application relates to the technical field of leakage detection, in particular to a method and system for detecting leakage of an anti-seepage layer in the construction of an artificial wetland, which determines the seepage time period in which each electrode grid may produce seepage by analyzing the changes in the potential difference data and humidity data of the electrode grid below the anti-seepage layer; based on the seepage time period, analyzes the coincidence of liquid diffusion between different electrode grids, and divides the electrode grid into several diffusion regions; divides the diffusion regions into suspected damage regions and diffusion interaction regions, and analyzes the area relationship between the suspected damage regions and the diffusion interaction regions to obtain the seepage damage probability of the diffusion region corresponding to each electrode grid; and according to the seepage damage probability, marks the leakage point region. Through the present application, the region where the anti-seepage layer may be damaged and diffused can be more accurately positioned, the accuracy of identifying the specific position of the anti-seepage layer where leakage occurs is improved, and the credibility of the leakage detection result of the anti-seepage layer is further improved.

A semiconductor device includes: a substrate; an epitaxial structure located on a side of the substrate; a gate electrode located on the side, facing away from the substrate, of the epitaxial structure. The gate electrode extends in a first direction parallel to a plane of the substrate and the gate electrode is in Schottky contact with the epitaxial structure; a gate connecting structure comprising a first gate connecting section and a second gate connecting section connected with each other, wherein the second gate connection section is electrically connected to at least part of the gate electrode. According to the semiconductor device, by providing a gate connecting structure, effect of resistance of a gate may be reduced, thereby increasing switching speed and improving a gain.

The embodiment of the invention discloses a transistor, a chip and electronic equipment. The transistor comprises a substrate, a channel, a first electrode, a gate electrode, a second electrode and a spacer layer, the channel is arranged on the substrate, the first electrode, the gate electrode and the second electrode are stacked along a first direction, the gate electrode is arranged around the channel, the first electrode is arranged on the substrate, and the first direction is perpendicular to the direction of the substrate; the spacer layer is arranged between the first electrode and the gate electrode, the spacer layer comprises a first spacer layer and a second spacer layer which are stacked along the first direction, the wet etching rate of the second spacer layer is lower than that of silicon dioxide (SiO2), and the dielectric constant of the first spacer layer is smaller than that of the second spacer layer. Therefore, while the corrosion resistance of the spacing layer is improved, the parasitic capacitance of the transistor is reduced, and the performance of the device is improved.