487 results about "Electrode Grid" patented technology

The present disclosure relates to the technical field of display chips. Disclosed are a full-color MicroLED and a manufacturing method therefor. The full-color MicroLED comprises a driving substrate, a first light-emitting layer, a first connecting layer, a second light-emitting layer, and a second connecting layer; the driving substrate comprises a first P-type semiconductor electrode transition layer; the first light-emitting layer comprises first light-emitting units and a second P-type semiconductor electrode transition layer; the first connecting layer comprises a first N-type semiconductor electrode transition layer, first N-electrode grids, and a third P-type semiconductor electrode transition layer; the second light-emitting layer comprises second light-emitting units and a fourth P-type semiconductor electrode transition layer; the second connecting layer comprises a second N-type semiconductor electrode transition layer and second N-electrode grids; a color conversion layer is provided at the position of the second connecting layer corresponding to some of the second light-emitting units. In the present disclosure, the driving substrate drives the light-emitting units on the first light-emitting layer and the second light-emitting layer to respectively emit green light and blue light, and then part of the blue light of the second light-emitting units is converted into red light by means of the color conversion layer, thereby achieving full-color light emission.

A photovoltaic module with a hidden bus bar is provided and comprises battery strings, the battery strings are a plurality of battery pieces connected in series in the X direction, and the plurality of battery strings are arranged in the Y direction; the battery pieces comprise positive electrode grid lines and negative electrode grid lines which are alternately arranged and are connected through positive electrode welding strips and negative electrode welding strips, and the battery pieces in the battery strings are connected through the positive electrode welding strips or the negative electrode welding strips; the bus bars are arranged along the Y direction and are connected with two adjacent battery strings; the bus bar comprises a bus bar main body and a plurality of extension parts which are arranged at intervals along the extension direction of the bus bar main body and are perpendicular to the main body, the extension parts are positioned on one side or two sides of the bus bar main body, and one ends of the extension parts extend out of the bus bar main body and are arranged above the first welding strip to be welded with the first welding strip; the insulating layer is arranged below the bus bar and is arranged on the second welding strip below the bus bar; wherein the first welding strip is a welding strip which is directly connected and welded with the bus bar, and the second welding strip is a welding strip which is not directly connected and welded with the bus bar. The photovoltaic module provided by the utility model does not have a sealing-off problem.

The invention discloses a crystalline silicon cell module, a preparation method and a photovoltaic system, and belongs to the technical field of solar cells. The crystalline silicon battery assembly comprises a plurality of crystalline silicon battery pieces, the plurality of crystalline silicon battery pieces comprise a first crystalline silicon battery piece and a second crystalline silicon battery piece, the light facing surface of the first crystalline silicon battery piece is provided with a first connecting piece, and the backlight surface of the second crystalline silicon battery piece is provided with a second connecting piece; the first connecting piece comprises a first electrode grid line, the first electrode grid line is electrically connected with the light-facing surface of the first crystalline silicon battery piece, the second connecting piece comprises a second electrode grid line, the second electrode grid line is electrically connected with the backlight surface of the second crystalline silicon battery piece, and the first connecting piece and the second connecting piece extend in opposite directions so as to be connected with each other; and the first electrode grid line is in contact connection with the second electrode grid line. The electrode grid lines between the two crystal silicon battery pieces are directly connected, so that no welding strip is needed for connection, the shading influence caused by the welding strip can be avoided, and the power of the module is improved.

The invention discloses a battery microstructure three-dimensional reconstruction simulation method and system based on an electrochemical model and computer equipment. The method comprises the following steps: acquiring a lithium ion battery electrode scanning sequence image, and acquiring a three-dimensional voxel model and an electrode grid chart; s2, acquiring key microstructure parameters of the electrode; s3, performing mesh generation on three-phase voxels in the electrode mesh chart to obtain a mesh file for finite element calculation; and S4, comparing the experimental data of the battery with the simulation data of the three-dimensional microstructure electrochemical model, adjusting the precision of the three-dimensional microstructure electrochemical model, and optimizing related parameters. According to the invention, three-phase accurate segmentation is carried out by using filtering and denoising, image enhancement and connectivity and a watershed segmentation algorithm, and a three-dimensional voxel model containing real particle morphology, cracks and pores and an electrode grid chart are reconstructed; the problems that in the prior art, a lithium ion battery microstructure simulation model is large in idealization deviation and inconsistent with a real structure, and consequently performance prediction is inaccurate are solved.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut is confined within the gate trench such that it does not extend beyond the walls of the gate trench as defined by gate spacer structures. Additionally, the gate dielectric does not form on any surface of the gate cut, such that the gate cut directly contacts the gate electrode.

The present disclosure provides a solar cell, a module and a system. The solar cell comprises a silicon substrate, first doped layers, second doped layers, positive electrode grid lines, negative electrode grid lines and a first PAD portion. The second doped layers are in recombination contact with the first doped layers at predetermined positions, so as to form leakage recombination contact structures. A first PAD point and a second PAD point of the first PAD portion are electrically and respectively connected to at least one positive electrode grid line and at least one negative electrode grid line.

A highly reliable semiconductor device is provided. The semiconductor device includes first to third transistors and a capacitor. In the first transistor, one of a source and a drain is supplied with a first signal, the other of the source and the drain is connected to a gate of the second transistor and one electrode of the capacitor, and a gate is supplied with a second pulse signal. In the second transistor, one of a source and a drain is supplied with a first pulse signal, and the other of the source and the drain is connected to the other electrode of the capacitor and one of a source and a drain of the third transistor. In the third transistor, the other of the source and the drain is supplied with the first potential, and a gate is supplied with a second signal that is an inverted signal of the first signal. The first pulse signal is a clock signal, and the second pulse signal has a duty ratio of 55% or lower.

The invention relates to a composition for transfer printing, a preparation method thereof and an electrode grid line preparation method, and relates to the technical field of photovoltaic cell manufacturing, and the composition for transfer printing comprises the following components by weight: 6-40% of polyvinyl alcohol; 0.05-5% of a plasticizer; 3-20% of a coalescing agent; 0.05 to 5% of a surfactant; 1-20% of a hydrophilic material; 0.01%-0.5% of a release agent; 0.01 to 1 percent of a flatting agent; 0.01 to 1 percent of a defoaming agent; and the balance of water. Through reasonable component proportion, the defects of an existing water-soluble film are optimized, and the dissolution speed, the environmental protection property, the mechanical property and the compatibility with a silicon wafer or conductive slurry of the water-soluble film are improved; by adding the surfactant, the hydrophilic material, the plasticizer and the coalescing agent, the flexibility, the tear resistance and the water solubility of the film are improved, so that the film has better mechanical properties, the defect of the traditional PVA film in the aspect of dissolution rate is overcome, and the quick water solubility, the good mechanical properties and the environmental protection property of the film are realized; and the transfer printing effect of the thin film and the adaptability of the thin film to a silicon wafer can be improved.

An array substrate includes sub-pixels, gate lines and data lines. The sub-pixels form pixel groups each including the first and second sub-pixels. The first sub-pixel includes a first transistor and a first electrode group including a first pixel electrode and a first commons electrode. The second sub-pixel includes a second transistor and a second electrode group including a second pixel electrode and a second common electrode. The gate lines form gate line groups each including a first gate line and a second gate line. At least part of the data lines each include: first data segments between a i-th column of sub-pixels and a (i+1)th column of sub-pixels, second data segments between a (i−j)-th column of sub-pixels and a (i−j-1)-th column of sub-pixels, and third segments. An overlapping are of the first pixel electrode and first common electrode equals that of the second pixel electrode and second common electrode.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention relates to a solar cell and a preparation method thereof, and a photovoltaic module, and the solar cell comprises a substrate which is provided with a first surface and a second surface, and the first surface and the second surface are opposite to each other; the first surface is provided with a groove; the first tunneling oxide layer is arranged in the groove of the first surface; the first doped polycrystalline silicon layer is arranged on one side, far away from the first surface, of the first tunneling oxide layer in the groove; the doping type of the first doped polycrystalline silicon layer is the same as that of the substrate; the first passivation anti-reflection layer is arranged on one side, far away from the first doped polycrystalline silicon layer, of the first surface; the first electrode grid line is arranged in the groove of the first surface, and the first electrode grid line penetrates through the first passivation anti-reflection layer to be in contact with the first doped polycrystalline silicon layer; the solar cell is capable of parasitic absorption; transmission channels of carriers are increased; and the ohmic contact between the electrode grid line and the doped polycrystalline silicon layer can be enhanced.

The invention belongs to the technical field of lead ion detection, and particularly relates to a black phosphorus field-effect tube lead ion detector and a use method thereof. The detector comprises an insulating substrate, a gate electrode layer, a gate electrode insulating layer, a sensitive layer, a source electrode and a drain electrode. The gate electrode layer is arranged on the insulating substrate, and the sensitive layer is arranged on the gate electrode insulating layer; particularly, the sensitive layer comprises a black phosphorus material, and noble metal particles are arranged on the surface of the sensitive layer. According to the invention, black phosphorus is used as a sensitive material of the field effect transistor, the black phosphorus and lead ions have good chemical matching property, and a stable coordination effect is formed through surface phosphorus atoms and lead ions, so that the conductivity of a channel is obviously changed; in addition, precious metal particles are introduced to the surface of the black phosphorus sensitive layer, so that the selective adsorption capacity of lead ions is enhanced. In a word, high-selectivity and high-sensitivity electrical detection of lead ions can be realized, and a high-performance field-effect tube sensor platform is provided for rapid monitoring of heavy metal pollutants.

The invention relates to the technical field of screen printing plates, in particular to a surface coating structure and process for prolonging the service life of a screen printing plate, and the surface coating structure comprises a screen frame, a metal net is arranged in the screen frame, a pattern area right opposite to a battery piece is arranged on the metal net, and a plurality of pattern openings used for printing electrode grid lines on the battery piece are formed in the pattern area. The pattern area comprises a long edge and a wide edge, the direction of the long edge of the pattern area is parallel to the moving direction of the scraper, the metal net comprises a P surface facing the battery piece and an S surface opposite to the battery piece, the P surface is covered with a printing PI film, the S surface is covered with a reinforcing PI film, and the reinforcing PI film is provided with a notch structure used for exposing a pattern opening. And a layer of reinforced PI film is additionally arranged on the S surface to wrap and protect the metal net, and when the metal net is extruded by the scraper, the reinforced PI film can share most pressure, so that the metal net is protected, and the overall service life is prolonged. And the gap structure ensures that the silver paste can normally penetrate through the pattern area for silk-screen printing.

Techniques are provided herein to form an integrated circuit having a semiconductor layer separating gate structures from source or drain regions instead of dielectric spacers. A FET (field effect transistor) includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around any number of nanoribbons of semiconductor material. The nanoribbons may extend in a first direction between source and drain regions while the gate structure extends over the nanoribbons in a second direction. A semiconductor layer separates the gate structure from contacting the source or drain region between adjacent nanoribbons. The semiconductor layer extends in a third direction between the gate structure and the source or drain regions and also between the nanoribbons and the source or drain regions. The source or drain regions may be epitaxially grown on the semiconductor layer.

The invention provides an electrode grid line and a preparation method thereof and conductive slurry, the electrode grid line comprises a seed layer and a base metal layer superposed on the upper layer of the seed layer, the base metal proportion in the conductive phase of the base metal layer is greater than 68%, the seed layer comprises a main grid and a seed layer fine grid, the base metal layer comprises base metal layer fine grids electrically connected with the seed layer fine grids in a one-to-one correspondence mode, at least one of the seed layer fine grids and the base metal layer fine grids is further provided with a plurality of contact pins, and the contact pins are distributed in the length direction of the corresponding fine grids at intervals. And the width of the contact pin in the line width direction of the fine grid is greater than the line width of the fine grid. The electrode grid line with the preset height is formed in a grid stacking mode, base metal is utilized by the base metal layer, the overall silver consumption amount of the electrode grid line is effectively reduced, the part, exceeding the width of the thin grid line where the contact pin is located, of the contact pin arranged on the thin grid line can be used for compensating printing precision deviation, the precision requirement for printing operation is reduced, and the contact performance is improved.

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

The invention relates to the technical field of TOPCon batteries, in particular to a TOPCon battery and a preparation method thereof. The preparation method of the TOPCon battery comprises the following steps: texturing a silicon wafer; performing boron diffusion doping on the front surface of the silicon wafer; carrying out acid washing and alkali washing polishing on the back surface of the silicon wafer; a first tunneling layer, a first doped polycrystalline silicon layer, a second tunneling layer and a second doped polycrystalline silicon layer are sequentially deposited on the back face of the silicon wafer, high-temperature annealing is conducted on the silicon wafer, and temporary protection layers are formed in an emitting electrode grid line area and a non-emitting electrode grid line area on the back face of the silicon wafer; performing film opening treatment on the temporary protection layer in a non-emitter grid line area; forming a textured structure on a non-emitter grid line area on the back surface of the silicon wafer; and pickling the silicon wafer. According to the technical scheme, the absorption of sunlight by the TOPCon cell can be improved, and the conversion efficiency of the TOPCon cell can be improved.

The present application relates to the technical field of leakage detection, in particular to a method and system for detecting leakage of an anti-seepage layer in the construction of an artificial wetland, which determines the seepage time period in which each electrode grid may produce seepage by analyzing the changes in the potential difference data and humidity data of the electrode grid below the anti-seepage layer; based on the seepage time period, analyzes the coincidence of liquid diffusion between different electrode grids, and divides the electrode grid into several diffusion regions; divides the diffusion regions into suspected damage regions and diffusion interaction regions, and analyzes the area relationship between the suspected damage regions and the diffusion interaction regions to obtain the seepage damage probability of the diffusion region corresponding to each electrode grid; and according to the seepage damage probability, marks the leakage point region. Through the present application, the region where the anti-seepage layer may be damaged and diffused can be more accurately positioned, the accuracy of identifying the specific position of the anti-seepage layer where leakage occurs is improved, and the credibility of the leakage detection result of the anti-seepage layer is further improved.

A semiconductor device includes: a substrate; an epitaxial structure located on a side of the substrate; a gate electrode located on the side, facing away from the substrate, of the epitaxial structure. The gate electrode extends in a first direction parallel to a plane of the substrate and the gate electrode is in Schottky contact with the epitaxial structure; a gate connecting structure comprising a first gate connecting section and a second gate connecting section connected with each other, wherein the second gate connection section is electrically connected to at least part of the gate electrode. According to the semiconductor device, by providing a gate connecting structure, effect of resistance of a gate may be reduced, thereby increasing switching speed and improving a gain.

The utility model discloses a Sic VDMOSFET structure with lower manufacturing cost, which relates to the technical field of semiconductor power devices and comprises a drain electrode, a conductive substrate layer arranged above the drain electrode, conductive epitaxial layers arranged on two sides of the upper end of the conductive substrate layer, a conductive column area arranged in the middle of the upper end of the conductive substrate layer, and a conductive electrode arranged in the conductive column area. A gate dielectric layer and a gate electrode are arranged above the conductive column region, a conductive polycrystalline silicon carbide layer is arranged in the gate dielectric layer, buffer structures are arranged above the two conductive epitaxial layers, and a conductive power supply region and a conductive well region are respectively arranged above the two buffer structures. According to the Sic VDMOSFET structure with the low manufacturing cost, the use stability of a Sic VDMOSFET device is improved, the resistance value of the Sic VDMOSFET device can be adjusted in time along with high temperature generated during power transmission, and meanwhile the problem that electric leakage loss occurs due to the fact that current is increased due to medium heating caused by movement of charged particles is solved.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first passivation layer, a second passivation layer and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode, the drain electrode, and the gate structure are disposed above the second nitride-based semiconductor layer. The first passivation layer is disposed above the second nitride-based semiconductor layer and covers the gate structure. The second passivation layer is disposed above the first passivation layer and in a region between the source and drain electrodes. The field plate is disposed above the second passivation layer and in the region between the source electrode and drain electrode, in which the field plate contacts at least one enclosed air gap above the first passivation layer.

This invention discloses a tunable broadband photodetector based on a Schottky junction, comprising: an N-type silicon substrate, a gate ferroelectric dielectric, a gate electrode, a source electrode, and a drain electrode; the source electrode, gate ferroelectric dielectric, and drain electrode are sequentially disposed on the N-type silicon substrate, and the gate electrode is disposed on the gate ferroelectric dielectric; the gate ferroelectric dielectric is made of hafnium oxide, a ferroelectric material, and the gate ferroelectric dielectric and the gate electrode together constitute a ferroelectric gate; the gate electrode is made of a transparent metal oxide. This invention utilizes silicon CMOS manufacturing technology and a simple device structure, greatly reducing the fabrication difficulty of silicon-based infrared detectors, and by leveraging the characteristic that the polarization intensity of ferroelectrics weakens under infrared light, extends the detection long-wavelength limit of silicon-based infrared detectors to the near-infrared band. This invention also discloses a method for fabricating and applying a tunable broadband photodetector based on a Schottky junction.

A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

The present invention specifically relates to an accumulation-type wide bandgap semiconductor trench MOSFET device structure and a method for preparing the same. The structure comprises at least a substrate, an epitaxial layer, a source P+ region, and a gate electrode; an N+ current channel is provided below the gate electrode trench, and N-accumulation-type channels and / or P-inversion channels are provided on both sides of the gate electrode trench. The N+ current channel is prepared by ion implantation and is located in the epitaxial layer. The N-accumulation-type channels and / or P-inversion channels are formed by the lateral diffusion effect during ion implantation of the N+ current channel. The present invention forms the N+ current channel through a trench bottom ion implantation process, and utilizes the lateral diffusion effect of this process during ion implantation to naturally form the N-accumulation-type channel and / or P-inversion channel. Furthermore, the channel doping concentration and thickness can be carefully controlled by controlling the mask thickness of the trench sidewalls during ion implantation of the N+ current channel, thereby achieving the purpose of enhancing channel mobility and reducing device on-resistance without the need for additional processes.

The present application relates to a semiconductor device and a semiconductor memory device. The semiconductor device of an embodiment includes an oxide semiconductor layer; a gate electrode; a gate insulating layer; a first electrode and a second electrode electrically connected to the oxide semiconductor layer; a first conductive layer provided at at least one of a position between the oxide semiconductor layer and the first electrode and a position between the oxide semiconductor layer and the second electrode, containing at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and including a first portion and a second portion, the first portion having a higher atomic concentration of the metal element than an atomic concentration of aluminum in the first portion, and the second portion having a higher atomic concentration of aluminum than an atomic concentration of the metal element in the second portion; and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer.

The invention discloses a solar photovoltaic anti-skid floor tile which comprises a plurality of anti-skid photovoltaic power generation floor tiles with different areas and the same structure, a mounting guide rail used for assembling and combining the multiple anti-skid photovoltaic power generation floor tiles and LED lamp strips assembled between gaps of the anti-skid photovoltaic power generation floor tiles. Through the micro-bump anti-skid structure on the surface of the tempered glass panel, the wet friction coefficient is increased while the low dust adhesion characteristic of a smooth surface is kept, and the anti-skid requirement is met. By adopting the back wiring battery technology, the electrode grid lines are hidden on the back surface of the battery piece, so that the surface of the floor tile presents a pure black grain-free integrated visual effect, and the anti-shielding performance is excellent. The bottom supporting plate adopts a lightweight composite material or aluminum alloy combined with a honeycomb mould pressing SMC forming process, the weight of a single floor tile is greatly reduced compared with that of a traditional scheme, and in cooperation with the design of heat dissipation holes of an inner cavity of a honeycomb structure, the floor tile has the strict requirements for high-strength bearing force and supporting of various environments, the service life is further prolonged, and the floor tile is suitable for popularization and application. And the materials can be completely recycled.

The utility model relates to a back contact type battery piece and a photovoltaic assembly, which are applied to the field of photovoltaic power generation, the back contact type battery piece comprises a battery piece, a fixing piece, a welding strip and insulation paste, and the battery piece comprises positive electrode grid lines and negative electrode grid lines which are alternately arranged and arranged in parallel; the welding strips are arranged on the fixing piece in a reciprocating and penetrating manner, and each welding strip is used for connecting all the positive grid lines or all the negative grid lines on a single battery piece; when the welding strip is connected with the positive electrode grid line, the insulation paste coats the negative electrode grid line located below the covering position of the fixing piece. And when the welding strip is connected with the cathode grid line, the insulation paste coats the anode grid line below the covering position of the fixing piece. By adopting the scheme, the welding strip is connected with the positive grid line or the negative grid line through the position of the protruding fixing piece, so that the problems that in the prior art, the reliability is poor due to the fact that the welding strip is directly fixed to the battery piece in a dispensing mode, and glue films are prone to flowing into the position below the welding strip to cause pseudo soldering during lamination welding are solved; and the problem of high cost caused by fixing the welding strip and the battery piece by adopting a hot melt adhesive is also avoided.

The embodiment of the present application provides a kind of N-type IBC battery negative electrode grid silver paste, N-type IIBC battery and preparation method thereof, wherein, the N-type IBC battery negative electrode grid silver paste provided in the embodiment of the present application includes organic auxiliary agent, silver powder, organic binder and doped glass powder, and the doping element of the doped glass powder is antimony, tellurium and tungsten.By doping antimony, tellurium and tungsten elements in glass powder, antimony element is the same as phosphorus, and the doping of N area can be increased;And tellurium and tungsten have the effect of dissolving silver, which can reduce the contact resistivity of silver grid line, improve the fill factor, thereby improving the photoelectric conversion efficiency of battery;Thus, the problem that the existing N-type IBC battery cannot form n+ region, so that the photoelectric conversion efficiency of N-type IBC battery is not good.

A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source / drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source / drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source / drain pattern and the gate electrode to electrically connect the source / drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source / drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.