117results about How to "High Power Handling Capability" patented technology

A SAW filter includes a piezoelectric substrate of Lithium Niobate or optionally Lithium Tantalate having a thickness of at least twice an acoustic wavelength. The piezoelectric substrate is bonded to a surrogate substrate of a silicon material. The surrogate substrate is characterized by a resisitivity of at least 100 ohm-cm and an expansion coefficient compatible with the piezoelectric substrate. A catalytic bonding film between the piezoelectric substrate and the surrogate substrate is formed from a first catalytic bonding film deposited onto a surface of the piezoelectric substrate and a second catalytic bonding film deposited onto a surface of the surrogate substrate. The piezoelectric substrate is bonded to the surrogate substrate through a compression force sufficient for providing a bonding at a normal temperature.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.

Method for synchronizing inverter units (INU11, INU12) that are connected in parallel and supply a motor, and a parallel connection arrangement, in which motor is either one winding, which is supplied by inverter units connected in parallel, or a plurality of parallel windings, in which each winding is supplied by its own inverter unit, in which parallel connection one inverter unit functions as a master and the others as slaves, in which method a telecommunications bus is arranged between the units, and in which each inverter unit has its own modulation cycle counter, which are synchronized with each other on the basis of telecommunications messages, preferably serial telecommunications messages. In the invention all the inverter units take into memory the value of their own modulation counter at the termination time of a telecommunications message (Mes2), the master inverter unit sends the reading of its own counter in the following message to the other inverter units, and the other inverter units correct the reading notified by the master on the basis of the readings of their own modulation counters in the direction that makes the counters operate as simultaneously as possible.