117results about How to "High Power Handling Capability" patented technology

A SAW filter includes a piezoelectric substrate of Lithium Niobate or optionally Lithium Tantalate having a thickness of at least twice an acoustic wavelength. The piezoelectric substrate is bonded to a surrogate substrate of a silicon material. The surrogate substrate is characterized by a resisitivity of at least 100 ohm-cm and an expansion coefficient compatible with the piezoelectric substrate. A catalytic bonding film between the piezoelectric substrate and the surrogate substrate is formed from a first catalytic bonding film deposited onto a surface of the piezoelectric substrate and a second catalytic bonding film deposited onto a surface of the surrogate substrate. The piezoelectric substrate is bonded to the surrogate substrate through a compression force sufficient for providing a bonding at a normal temperature.

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

A method of fabricating AlGaN / GaN enhancement-mode heterostructure field-effect transistors (HFET) using fluorine-based plasma immersion or ion implantation. The method includes: 1) generating gate patterns; 2) exposing the AlGaN / GaN heterostructure in the gate region to fluorine-based plasma treatment with photoresist as the treatment mask in a self-aligned manner; 3) depositing the gate metal to the plasma treated AlGaN / GaN heterostructure surface; 4) lifting off the metal except the gate electrode; and 5) high temperature post-gate annealing of the sample. This method can be used to shift the threshold voltage of a HFET toward a more positive value, and ultimately convert a depletion-mode HFET to an enhancement-mode HFET (E-HFET).

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN / GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.

A power over Ethernet controller supporting a plurality of powering modes, the power over Ethernet controller comprising: a pair of power sourcing equipments; and a control circuit; the control circuit being operative to control each of the pair of power sourcing equipment units in one of a first mode and a second mode, the first mode comprising operating the pair of power sourcing equipments as a single power sourcing equipment operable to power a single powered device over communication cabling, and the second mode comprising operating each of the power sourcing equipments of the pair independently so as to each be operable to power an associated powered device over communication cabling.

Method for synchronizing inverter units (INU11, INU12) that are connected in parallel and supply a motor, and a parallel connection arrangement, in which motor is either one winding, which is supplied by inverter units connected in parallel, or a plurality of parallel windings, in which each winding is supplied by its own inverter unit, in which parallel connection one inverter unit functions as a master and the others as slaves, in which method a telecommunications bus is arranged between the units, and in which each inverter unit has its own modulation cycle counter, which are synchronized with each other on the basis of telecommunications messages, preferably serial telecommunications messages. In the invention all the inverter units take into memory the value of their own modulation counter at the termination time of a telecommunications message (Mes2), the master inverter unit sends the reading of its own counter in the following message to the other inverter units, and the other inverter units correct the reading notified by the master on the basis of the readings of their own modulation counters in the direction that makes the counters operate as simultaneously as possible.

A single trigger / shunt coil is utilized for combined induced magnetic field triggering and shunt impedance. The single coil connected in parallel with the high temperature superconducting element, is designed to generate a circulating current in the parallel circuit during normal operation to aid triggering the high temperature superconducting element to quench in the event of a fault. The circulating current is generated by an induced voltage in the coil, when the system current flows through the high temperature superconducting element.

A waveguide orthomode transducer. In a first layer a turnstile junction having a main waveguide and four waveguide ports, and four hybrid tees each have an e-port, two opposed side-ports, and an h-port. The hybrid tees are ring-arranged around the turnstile junction so the waveguide ports each communicate with one h-port, so adjacent hybrid tees inter communicate with their respective side-ports, and so the e-ports form two sets of opposed e-ports. In a second layer two h-plane power dividers / combiners each have an axial-port and two opposed side-ports. The h-plane power dividers / combiners are arranged so their respective side-ports communicate with different ones of the two sets of opposed e-ports and so their axial-ports are polarization ports. This permits a single signal with two fundamental orthogonally polarized modes to enter the main waveguide and exit separated at the polarization ports vice versa.

The present invention improves the geometry of ferrite circulators in order to increase the average power handling by decreasing the temperature rise in the ferrite and associated adhesive bonds. Embodiments of the present invention utilize dielectric attachments on the sides of the ferrite element, which maximizes the area of contact and minimizes the path length from the ferrite element out to the thermally conductive attachments.

A SAW filter includes a piezoelectric substrate of Lithium Niobate or optionally Lithium Tantalate having a thickness of at least twice an acoustic wavelength. The piezoelectric substrate is bonded to a surrogate substrate of a silicon material. The surrogate substrate is characterized by a resisitivity of at least 100 ohm-cm and an expansion coefficient compatible with the piezoelectric substrate. A catalytic bonding film between the piezoelectric substrate and the surrogate substrate is formed from a first catalytic bonding film deposited onto a surface of the piezoelectric substrate and a second catalytic bonding film deposited onto a surface of the surrogate substrate. The piezoelectric substrate is bonded to the surrogate substrate through a compression force sufficient for providing a bonding at a normal temperature.

Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a −60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.