The application provides a data reading circuit of an MRAM
chip, comprising: a to-be-tested storage unit, a first gating
transistor connected in series with the to-be-tested storage unit, a reference unit, a second gating
transistor connected in series with the reference unit, and a readout
amplifier, wherein the reference unit has three optional reference resistance branches, including a working mode
branch, a first test mode
branch and a second test mode
branch, the working mode branch is used for reading data of the to-be-tested storage unit, the first test mode branch is used for screening out fixed failure units and high-resistance state out-of-range failure units with an open-
circuit failure type, and the second test mode branch is used for screening out fixed failure units and low-resistance state out-of-range failure units with a short-
circuit failure type.