135 results about "Planar process" patented technology

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

Device 60 in FIG. 3 has junctions 86 each with a lateral portion 90 and a second portion 92 extending upward toward the surface 12 from the lateral portion 90. The lateral portions 90, as illustrated in FIG. 3, are more or less formed along a plane parallel with the surface 12. The upwardly extending portions 92 include characteristic curved edges of the diffusion fronts which are associated with the planar process. With the regions 80 and 82 each having relatively high net dopant concentrations of different conductivity types, each lateral junction portion 90 includes a relatively large sub region 96 which extends more deeply into the layer 10. When compared to other portions of the junctions 86, the subregions 96 are characterized by a relatively low breakdown voltage so that ESD current is initially directed vertically rather than laterally.

A highly sensitive optical sensor element, and a switch element such as a sensor driver circuit are formed on the same insulating substrate by using an LTPS planar process to provide a low cost area sensor (optical sensor device) incorporating the sensor driver circuit and the like or an image display device incorporating the optical sensor element. As an optical sensor element structure, one electrode of the sensor element is manufactured with the same film of the polycrystalline silicon film that is an active layer of the switch element constituting a circuit. A photoelectric conversion unit for performing photoelectric conversion is made of an amorphous silicon or a polycrystalline silicon film of an intrinsic layer. A structure in which the amorphous silicon of the photoelectric conversion unit and the insulating layer are sandwiched between two electrodes of the sensor element is adopted.

Pixels in a focal plane array are defined by controlled variation of the Fermi energy at the surface of the detector array. Varying the chemical composition of the semiconductor at the detector surface produces a corresponding variation in the surface Fermi energy which produces a corresponding variation in the electric field and electrostatic potential in the bulk semiconductor below the surface. This defines pixels by having one Fermi energy at the surface of each pixel and a different Fermi energy at the surface between pixels. Fermi energy modulation can also be controlled by applying an electrostatic potential voltage V1 to the metal pad defining each pixel, and applying a different electrostatic potential voltage V2 to an interconnected metal grid covering the gaps between all the pixel metal pads. Methods obviate the need to etch deep trenches between pixels, resulting in a more manufacturable quasi-planar process without sacrificing performance.

Nanostructured thermoelectric elements are made from planar uniwafer processing methods. The method includes producing either n-type or p-type thermoelectric uniwafer structure bearing nanostructure material embedded in a low thermal conductivity fill material. The method further includes partially cutting the uniwafer structure to form a plurality of chip structures separated by trenches. The method includes filling the trenches with the fill material to surround the nanostructure material within each chip structure. The method further includes additionally planar processing to form both frontend and backend conductive contact layers respectively coupled to frontend regions and backend regions of the chip structures. Additionally, the modified thermoelectric uniwafer structure is cut to turn the chip structures to bulk-sized nanostructured thermoelectric legs, each bulk-sized nanostructured thermoelectric leg being wrapped around by the fill material and ready for assembling thermoelectric modules.

The present invention is method and device for detecting the microwave dielectric characteristic of ferroelectric film. The device includes substrate, measured ferroelectric film on the substrate, coplanar waveguide line including main transmission line and earthing areas separated on two sides on the film, and coplanar quarter-wave open-circuited line on the film and including transmission line connected to the main transmission line and earthing areas separated on two sides. Owing to the coplanar quarter-wave open-circuited line to form the resonant peak, the dielectric characteristic of the measured film may be obtained easily. The pattern for detection of the ferroelectric film may be formed in once forming process. Therefore, compared with available technology, the present invention has simple principle and easy device making and assembling, and is convenient and practical.

The invention discloses a bionic hair-type silicon micro-gyroscope for angular velocity sensing. The bionic hair-type silicon micro-gyroscope is composed of upper polymer hair, a middle silicon micro-sensor and a bottom glass substrate equipped with a circuit, wherein the middle silicon micro-sensor comprises a circular mass block and an annular mass block with a same circle center as the circular mass block; two torsion beams are arranged between the circular mass block and the annular mass block; the upper polymer hair is adhered onto the center of the circular mass block; and the circumferential lateral part of the annular mass block are uniformly provided with a plurality of comb groups and square wave supporting beams which are arranged in a staggered way. The bionic hair-type silicon micro-gyroscope is novel in structure, has high sensitivity and is compatible with conventional planar process; and compared with a simple conventional planar structure, the arrangement of the upper polymer hair is favorable for enlarging the Coriolis effect and improving structure sensitivity.

The present application discloses a method for manufacturing a semiconductor device, comprising: forming a local buried isolation dielectric layer in a semiconductor substrate; forming a fin in the semiconductor substrate and on top of the local buried isolation dielectric layer; forming a gate stack structure on a top surface and side surfaces of the fin; forming source/drain structures in portions of the fin which are on opposite sides of the gate stack structure; and performing metallization. A conventional quasi-planar top-down process is utilized in the present invention to achieve a good compatibility with the CMOS planar processes, easy integration, and suppression of short channel effects, which promotes the development of MOSFETs having reduced sizes.

The invention discloses a silica-based surface electronic emitter and a preparation method thereof. The emitter deposits a SiO2 or Al2O3 thin film layer at the front of an 'n' type silicon substrate, a gate electrode is deposited on the SiO2 or Al2O3 thin film layer and an ohmic contact electrode is deposited at the back of the silicon substrate; the producing method comprises the following steps: an 'n' type silicon chip is washed firstly; a SiO2 or Al2O3 thin film is deposited on the silicon chip by a thermal oxidation method or a chemical vaporous deposition method or an evaporation method or a sputtering method or a sol-gel method; the gate electrode is sputtered on the SiO2 or Al2O3 thin film, and the ohmic contact electrode is sputtered at the back of the silicon substrate. The silica-based surface electronic emitter of the invention has higher electronic emission energy and good performance for high field emission, can be used for producing a field emission display, has simple producing technique and is compatible with the existing mature silicon device planar technique.

The invention provides an out-plane piezoelectric type hemispheric micro-gyroscope and a preparation method thereof. The out-plane piezoelectric type hemispheric micro-gyroscope comprises a monocrystalline silicon substrate, a miniature hemispheric harmonic oscillator, a central fixed support pillar, a common electrode, a uniformly distributed film piezoelectric body and a uniformly distributed signal electrode. According to the invention, the hemispheric structure is adopted as a harmonic oscillator, so that great effective vibration displacement is obtained, and detection effect for Coriolis effect can be enhanced; the common electrode, the film piezoelectric body and the signal electrode are manufactured by adopting an MEMS planar process, so that the manufacturing precision is high, and the structural degree of symmetry of the micro-gyroscope can be improved; the out-plane driving and the detection method are adopted, so that interconversion between out-plane force and in-plane can be realized, and Coriolis effect vertical to the direction of the substrate can be detected; the piezoelectric type driving and the detection method are adopted, miniature capacitance space needed by electrostatic micro-gyroscope is not needed, and meanwhile, the problems of stray capacitance, electrostatic adherence and the like are avoided; the technology is simple, the integrated degree is high, and batch production can be realized.

The present application discloses a semiconductor device structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising a local SOI structure having a local buried isolation dielectric layer; forming a fin on the silicon substrate on top of the local buried isolation dielectric layer; forming a gate stack structure on the top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof is simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated, therefore, short channel effects are suppressed desirably, and MOSFETs are boosted to develop towards a trend of downscaling size.

Quality of one-surface planar processed group 3 nitride wafers depends upon a direction of pasting of wafers on a polishing plate. Low surface roughness and high yield are obtained by pasting a plurality of group 3 nitride as-grown wafers on a polishing plate with OFs or notches facing forward (f), backward (b) or inward (u) with thermoplastic wax having a thickness of 10[mu]m or less, grinding the as-grown wafers, lapping the ground wafers, polishing the lapped wafers into mirror wafers with a bevel of a horizontal width of 200[mu]m or less and a vertical depth of 100[mu]m or less.

The invention discloses a method for forming a totally-enclosed gate structure. The method is used for manufacturing FinFET devices, and comprises forming a gate dielectric, Fin and a gate in steps by use of a planar process and connecting the lower end of the gate surrounding the Fin with a substrate to form the totally-enclosed gate structure. As the gate dielectric is quite thin and the lower end of the gate is connected with the substrate, the gate is enabled to effectively control channels from all sides still in a totally enclosing form. As a result, the method for forming the totally-enclosed gate structure succeeds in solving the problems of complex process and high cost in the prior art while guaranteeing the desired device characteristics. The method is simple and convenient, and compatible with the existing integrated circuit planar process, and has the advantages of low cost, easy implementation and the like.

The invention discloses an electric pumping silica-based MgxZn1-xO film ultraviolet random laser and a manufacturing method thereof. The random laser has a structure as follows: the MgxZn1-xO (x is more than 0 and less than or equal to 0.35) film, a dielectric film and an electrode are deposited on the front face of a silica substrate from bottom to top in sequence and an ohmic contact electrode is deposited on the back face of the silica substrate, wherein the dielectric is silicon oxide, aluminum oxide or silicon nitride. The silica-based random laser does not need a traditional laser cavity resonator and has simple preparation technique. In addition, equipment used is compatible with the prior mature planar technology of silica devices. Therefore, the silica-based random laser has potential application in respect of phoelectron integration and the like.

It is a bistable electromagnetic micro machinery relay, which combines the separate process of moving electrode system, plane coil, contact electrode system and magnetic core. The moving electrode system comprises moving electrode, wring beam, contact and frame; the plane coil and contact electrode system are made on the silicon underlay; the moving electrode system is fixed through the frame on the silicon underlay of plane coil and contact electrode; the constant magnetic metal sticks tightly to the surface of the permalloy magnetic core. This relay uses electromagnetic metal to change the magnetic direction of the moving electrode and to turn in the stable on or off status.

An electronic circuit device having a silicon substrate is provided comprising: a silicon substrate having a semiconductor element and a recess; and at least one passive element which is formed by a process different from a silicon planar process by which the semiconductor element is formed. In the electronic circuit device, the passive element is entrenched in the recess of the silicon substrate, and the semiconductor element formed on the silicon substrate is electrically connected to the passive element.

In one embodiment, the present invention includes an apparatus having a protection circuit to provide protection from transient surges. The protection circuit may include a silicon controlled rectifier (SCR) that is formed on a substrate via a planar process, along with one or more circuits to be protected by the protection circuit.

The invention relates to a based on metal molybdenum of the substrate, field emission electron-emitting cathode array and a manufacturing method thereof. The field-induced electron-emitted cathode array comprises a plurality of metal molybdenum pointed cones consistent in morphology and regularly arranged. The metal molybdenum is subjected to plane manufacturing technology during the metal molybdenum substrate machining process, so that the array of pointed cones is high in morphology consistence. Through adjusting the machining parameters of the metal molybdenum substrate machining process, the morphology of the pointed cones can be conveniently changed. In this way, according to requirements of field emission currents, corresponding pointed cone arrays can be manufactured and machined for large-scale production. According to the technical scheme of the invention, through the metal molybdenum substrate machining process, pointed cone arrays are high in morphology consistence, and the number of simultaneously transmitted pointed cones is increased during operation. The density of the field emission current is further increased. Therefore, a large-area pointed cone array, which is good in shape consistency, can be obtained.