The invention discloses a downward-source MOS device based on a plane MOS process and a preparation method, and relates to the technical field of
semiconductor devices, the downward-source MOS device comprises a
semiconductor substrate, an active region and a gate region, the active region is formed on the surface of the
semiconductor substrate, and the gate region is located above the active region; a drain
electrode and a source
electrode are arranged in the active region, the drain
electrode on one side is electrically connected to the front surface of the
chip through a forward
metal electrode, and the forward
metal electrode is located in the gate region; the source electrode on the other side is communicated with the semiconductor substrate through the electrode connection area and forms good
ohmic contact, and a substrate
metal electrode is arranged at the bottom of the semiconductor substrate. According to the invention, the
layout is reasonable, the structure is compact, the process cost is low, compared with a Diodes heterostructure, two
mask steps of a main groove and a field plate groove are reduced, and stress and defects caused by groove filling are avoided; the
chip is simple in structure and high in integration level, compared with an Infineon packaging-level source bottom, source
interconnection is directly achieved in the
chip, the multi-device stacking design is supported, and the occupied space of a bonding pad and a lead channel is saved.