189 results about "Heterojunction field effect transistor" patented technology

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

Semiconductor devices, e.g., heterojunction field effect transistors, fabricated with silicon-germnanium buffer layer and silicon-carbon channel layer structures. The invention provides a method of reducing threading defect density via reducing germanium content in a SiGe relaxed buffer layer on which a strained silicon channel layer is formed, by forming the strained silicon channel layer of a silicon-carbon alloy, e.g., containing less than about 1.5 atomic % C substitutionally incorporated in the Si lattice of the alloy.

A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Embodiments disclosed herein include electronic device designs based upon electronic properties of Group III-N materials and quantum-mechanical effects of specialized heterostructures. Such electronic device designs may include, for example, heterojunction field-effect transistors (HFETs) and high-electron-mobility transistors (HEMTs). The design concepts permit high power, high-frequency, and high-temperature operation of advanced electronic circuits, including devices for radar, collision-avoidance systems, and wireless communications. Designs disclosed may include one or more AlN layers and/or one or more SMASH superlattice barriers combined with one or more n-type delta-doped regions. Alternately, in certain embodiments, one or more AlN layers and one or more SMASH superlattice barriers may be combined without the n-type delta-doped regions.

This invention relates to a wide band-gap GaN-base heterojunction field effect transistor structure including: a substrate, a high temperature AlN nucleating layer on the substrate, an AlInGaN supper lattice buffer layer processed on the nucleating layer, a non-intentional or intentional doped GaN high resist layer processed on the buffer layer, a non-intentional doped high transfer rate GaN layer processed on the high resist layer and an AlN insertion layer set on the high transfer rate GaN layer and a non-intentional doped or n-type doped AlInGaN layer set on the AlN insertion layer.

In the nitride semiconductor heterojunction field effect transistor of the present invention, the floating gate layer (32), as the third layer, is formed between the control gate electrode (34) and the AlGaN layer (11), and the potential for the electrons in the AlGaN layer (11), which is substantially neighboring the floating gate layer (32), is able to be substantially high, and then the channel is able to be depleted. Hence, no current can be flowed through the channel (no drain current) at the time of no gate voltage, as so-called stable normally-off operation can be obtained.

Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties.

A nitride based hetero-junction field effect transistor comprises a high resistance nitride semiconductor layer formed on a substrate, an Al-doped GaN layer formed on the high resistance nitride semiconductor layer and having an Al content of 0.1˜1%, an undoped GaN layer formed on the Al-doped GaN layer, and an AlGaN layer formed on the undoped GaN layer such that a two-dimensional electron gas (2DEG) layer is formed at an interface of the undoped GaN layer. With the Al-doped GaN layer and the undoped GaN layer grown on the high resistance GaN layer having low crystallinity, crystallinity of the GaN layer is enhanced, and thus electrical characteristics of DC and RE of an HEET device are remarkably improved due to enhanced carrier mobility.

The invention discloses a gallium nitride-based hetero-junction field effect transistor with a back electrode structure. The gallium nitride-based hetero-junction field effect transistor mainly consists of a substrate, an aluminum nitride nucleating layer, a P-type aluminum-indium-gallium-nitrogen buffering layer, a gallium nitride channel layer, an aluminum nitride inserting layer and an aluminum-indium-gallium-nitrogen barrier layer in sequence from bottom to top; a source electrode, a drain electrode and a gate electrode are formed on the barrier layer; the source electrode and the drain electrode form ohmic contact with the barrier layer; the gate electrode and the barrier layer are in Schottky contact; and the gallium nitride-based hetero-junction field effect transistor further comprises the back electrode in contact with the substrate. The back electrode in the gallium nitride-based hetero-junction field effect transistor provided by the invention modulates potential distribution of a device buffering layer, so as to increase potential difference between the two-dimensional electron gas channel and the P-type aluminum-indium-gallium-nitrogen buffering layer. Therefore, two-dimensional electron gas in the channel and the P-type impurities in the buffering layer are entirely consumed, so that the electric field distribution of the device channel is more uniform, and the breakdown voltage of the device is improved.

The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same.

The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an Al_xGa_1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an Al_yGa_1-yN barrier layer with a composition of Al being y (0<y≦1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.

A heterojunction field effect transistor operative from the micro wave band to the millimeter wave band has a gate recess structure formed in a manner such that its eye-empty areas have a significant effect on the voltage durability of the transistor. The eye-empty areas extend from a gate electrode to a source electrode as well as to a drain electrode and are formed by at least two material layers having different impurity concentrations, thereby making it possible to obtain an improved heterojunction field effect transistor having a reduced series resistance and an increased voltage durability.

The invention is a GaN-based HFET structure, which comprises an underlay, a low-temperature GaN nucleating layer which is set on the underlay; a resistive formation doped or unintended doped with GaN, which is made on the upside of the low-temperature GaN nucleating layer; an unintended doped high mobility GaN layer, which is set on the upside of the resistive formation unintended doped with GaN; an aluminum nitride interposed layer, which is made on the unintended doped high mobility GaN layer; a component step change AlxInyGazN layer unintended doped or doped in type N, which is set on the aluminum nitride interposed layer.

In a heterojunction FET in which source and drain areas are formed by carrying out high temperature annealing process after carrying out ion implantation in areas to be formed into source and drain areas, conventionally, the N-type carrier supply layer and the N-type active layer are doped with Si. In place of doping with Si, doping with Se or Te is adopted. Thereby, in high temperature annealing process for activating the ion implanted areas, which serves as source and drain areas, unlike the Si donor, inactivation of donor due to reaction with F-atoms occurs scarcely with respect to the diffusion of F-atoms on the surface of the epitaxial substrate, which adhered during the process. Further, since the Se and Te are impurities from VI-family, when the Se or Te occupies any grid position of atoms from III-family or V-family, the Se or Te serves as the donor. Accordingly, a high performance heterojunction FET of little deterioration of the FET characteristics can be obtained.

A heterojunction field effect transistor includes a laminated body. The laminated body includes a channel layer of GaN, an electron supply layer of AlN or Al_xGa_1-xN (0.6≦x<1) formed on the channel layer, and a cap layer of GaN formed on the electron supply layer.

The invention relates to a heterojunction field effect transistor based on a channel array structure. The heterojunction field effect transistor comprises a heterojunction which comprises a first semiconductor layer and a second semiconductor layer which are stacked from top to bottom; a two-dimensional electron gas is formed on the interface of the first semiconductor layer and the second semiconductor layer; a source electrode, a drain electrode and a grid electrode are arranged on the first semiconductor layer; the grid electrode is arranged between the source electrode and the drain electrode; and more than one channels are formed in the heterojunction under the grid electrode, and two ends of the channel respectively point to the source electrode and the drain electrode. In the invention, the structural design based on the channel array is adopted, and an annular gate structure is formed by covering a gate metal on the top part of the channel and the side walls on two sides, so that the capability of modulating the channel is strengthened. The heterojunction field effect transistor is suitable for all semiconductor electron devices working based on the two-dimensional electron gas on the heterojunction node interface, and various requirements of practical application can be met simultaneously.

The invention discloses a source-field-plate heterojunction field-effect transistor and a manufacturing method, and mainly solves the problems of low breakdown voltage and low power gain in the conventional field-plate technology. The source-field-plate heterojunction field-effect transistor comprises a substrate (1), a transition layer (2), a potential barrier layer (3), a source electrode (4), a drain electrode (5), a passivating layer (6), a Gamma-shaped grid (8) and a protective layer (11), wherein the passivating layer (6) is provided with a groove (7); a part of the Gamma-shaped grid (8) is positioned in the groove (7), and the other part of the Gamma-shaped grid (8) is positioned at the upper part of the passivating layer (6); the passivating layer (6) between the Gamma-shaped grid (8) and the drain electrode (5) is provided with a source field plate (9) and n floating metal field plates (10); the source field plate (9) is connected with the source electrode (4); the floating metal field plates are same in length, and the distances among the field plates are same; and the Gamma-shaped grid (8), the source field plate (9) and the n floating metal field plates (10) are manufactured by using a same metal deposition process so as to form the source-field-plate heterojunction field-effect transistor. The source-field-plate heterojunction field-effect transistor and the method have the advantages of high breakdown voltage, little grid-drain feedback capacitance, high power grain and simpleness for process, and is applicable to high-frequency and large-power III-V compound microwave power devices.

The invention provides an enhanced GaN heterojunction field effect transistor based on metal oxide semiconductor (MOS) control and belongs to the technical field of power semiconductor devices. The enhanced GaN heterojunction field effect transistor comprises a monolithic integrated low-voltage MOS tube and a depletion mode GaN heterojunction field effect transistor, wherein the drain of the MOS tube is connected with the source of the depletion mode GaN heterojunction field effect transistor; the grid of the MOS tube and the grid of the depletion mode GaN heterojunction field effect transistor are connected with each other or the grid of the GaN heterojunction field effect transistor is connected with the source of the MOS tube; and the MOS tube and the depletion mode GaN heterojunction field effect transistor are isolated from each other by using a medium isolation slot. In the enhanced GaN heterojunction field effect transistor based on MOS control, transformation from the depletion mode GaN heterojunction field effect transistor to the enhanced GaN heterojunction field effect transistor is realized by controlling an on/off state of the low-voltage MOS tube connected in series with the depletion mode GaN heterojunction field effect transistor; the enhanced GaN heterojunction field effect transistor has the normally off characteristic of the low-voltage MOS tube and the advantages of high-voltage resistance, low-conductivity resistance and the like of the depletion mode GaN heterojunction field effect transistor, has good frequency characteristic and high output power and density, and is applicable to the high-frequency and high-power fields.

The invention discloses a vertical GaN heterojunction field-effect transistor with a P type GaN island. The field-effect transistor comprises an AlGaN barrier layer, wherein a source electrode and a grid electrode are arranged on the AlGaN barrier layer, and a GaN channel layer, a p-GaN current blocking layer, an n-GaN buffer layer, an n+-GaN substrate and a drain electrode are arranged under the AlGaN barrier layer in sequence. A hole with the caliber of LAP is formed in the center of the p-GaN current blocking layer and nested to the n-GaN buffer layer, the p-GaN island is arranged in the n-GaN buffer layer, and the p-GaN island is located between the p-GaN current blocking layer and the n+-GaN substrate. In the GaNPI-VHFET, by using the p-GaN island layer, extra p type impurities are introduced into the n-GaN buffer layer, and the n-GaN buffer layer area is exhausted in the off state, so that the buffer area is equivalent to an intrinsic region during voltage resistance. Therefore, the problem that the vertical electric field intensity is continuously decreased when current moves far away from an interface of the p-GaN current blocking layer and the n-GaN buffer layer is solved to increase breakdown voltage of a device. Meanwhile, leaked current of the drain electrode is also decreased in the off state.