11 results about "Drain resistance" patented technology

The utility model relates to the technical field of welding equipment detection, in particular to a welding table point inspection tester circuit, a welding table point inspection tester and a welding table. The utility model relates to a welding station spot inspection tester circuit, which is characterized by comprising a temperature detection circuit, a drain voltage detection circuit, a leakage resistance detection circuit, a multi-channel switching module, a display module and a central control unit, and the central control unit is used for receiving test data from the temperature detection circuit, the drain voltage detection circuit and the drain resistance detection circuit, judging the performance of the soldering station according to the test data, outputting a corresponding signal to control the multi-channel switching module to perform test switching, and outputting and displaying a detection result through the display module. According to the scheme, by integrating multiple functions, comprehensive monitoring of the performance of the welding table is achieved. Through efficient cooperation of all the modules, detection of the performance of the welding table is more efficient and accurate, and operation is easy and convenient.

A non-volatile memory device includes: a resistive switching layer; a gate on the resistive switching layer; a gate oxide layer between the resistive switching layer and the gate; and a source and a drain on the resistive switching layer and spaced apart from each other. The resistance value of the resistive switching layer changes based on the illuminance of light illuminating the resistive switching layer and remains at the changed resistance value.

The application discloses a leakage current processing circuit, a pixel circuit, a display panel and a display device. The leakage current processing circuit comprises: a resistance unit, an input end of the resistance unit being coupled to a first source-drain electrode of a thin film transistor, and an output end of the resistance unit being coupled to a pixel electrode; and an operational amplifier unit, an input end of the operational amplifier unit being coupled to the resistance unit, and an output end of the operational amplifier unit being coupled to the output end of the resistance unit through a target capacitor. The operational amplifier unit converts a sampling voltage of a sampling resistor in the resistance unit into a first leakage voltage in response to the leakage current of the resistance unit, inverses the first leakage voltage to obtain a second leakage voltage, and outputs the second leakage voltage to the target capacitor, so that the target capacitor offsets part of a pixel electrode voltage output from the output end of the resistance unit to the pixel electrode. In this way, the pixel voltage input to the pixel electrode is reduced, and the effect of improving the leakage of the thin film transistor is achieved.

The invention discloses a method and a system for measuring the under-gate electron mobility of a high-electron-mobility transistor, and mainly relates to the technical field of integrated circuit engineering. Comprising the following steps: testing gate-source currents corresponding to different gate-source voltages to obtain a first relational graph; based on the first relation graph, performing linear fitting to obtain gate-source resistance; testing gate-drain currents corresponding to different gate-drain voltages to obtain a second relational graph; based on the second relation graph, performing linear fitting to obtain gate-drain resistance; calculating the total resistance of the channel; and calculating the under-gate electron mobility. The method has the beneficial effects that the interference of parasitic resistance and contact resistance on migration rate extraction is effectively eliminated, and the calculation accuracy is improved.

The present application belongs to the technical field of power integrated circuit, and particularly relates to a method for establishing and simulating a lateral high-voltage device equivalent circuit model. The circuit model comprises: a field effect transistor; a drain resistance, one end of which is connected to the drain of the field effect transistor and the second end of which is used as the drain of a high-voltage device; a source resistance, one end of which is connected to the source of the field effect transistor and the second end of which is used as the source of a high-voltage transistor; a body diode, which is connected in series with a diode cathode through a parallel network of a cathode resistance and an inductor, the anode of which is connected to the source of the high-voltage transistor, and the other end of the cathode resistance is connected to the drain of the high-voltage device; a first current source, one end of which is connected to the drain of the high-voltage device and the other end of which is connected to the source of the high-voltage device; and a simulation model, which uses a voltage control resistance value relationship to correct the resistance value of an external resistance. Compared with a traditional model, the resistance expression of the present application has a clear physical meaning, effectively improves the simulation accuracy of the lateral high-voltage device model, and has better convergence.

The application relates to a high-power-supply-rejection low-voltage-difference linear voltage stabilizer based on gate capacitance offset, which comprises an error amplifier, a power tube M P , a feedback network R1 and R2, a load capacitor C L , a frequency compensation capacitor C M and a gate capacitor offset circuit; the output end of the error amplifier, the output end of the gate capacitor offset circuit, the gate of the power tube M P and one end of the frequency compensation capacitor C M are connected; the other end of the frequency compensation capacitor C M , the drain of the power tube M P , one end of the resistor R1, one end of the load capacitor C L and the V OUT end are connected; the source of the power tube M P is connected to the V IN end; the other end of the load capacitor C L , one end of the resistor R2 and the ground end GND are connected; the other end of the resistor R1, the other end of the resistor R2 and the non-inverting input end V FB of the error amplifier are connected. The application changes the equivalent capacitance of a node by introducing a gate capacitor offset circuit at the output end of the error amplifier, reduces the input-to-output gain and improves the power supply rejection capability.

The application relates to a method for extracting key parameters of an enhancement-mode GaN device based on a depletion-mode GaN HEMT, belonging to the technical field of microelectronic research, and a same-size depletion-mode D-mode device is prepared beside an enhancement-mode E-mode device; since the size of the enhancement-mode E-mode device is completely same as that of the depletion-mode D-mode device, gate-source resistance and gate-drain resistance of the enhancement-mode device can be directly obtained through the depletion-mode device, and the key parameters of the enhancement-mode device can be quickly, conveniently and accurately extracted; since the depletion-mode device and the enhancement-mode device are adjacent, the gold-semiconductor contact resistance error value caused by uneven etching of P-GaN can be eliminated, and the accuracy of extraction of the key parameters of the device is improved; and the method for extracting the key parameters is realized based on a conventional structure and electrical test data, and does not need to introduce a complex structure and a destructive test.

This invention discloses a parameter extraction method for the equivalent circuit model of a GaN HEMT device, comprising at least the following steps: Step S1: Modeling the GaN HEMT device as a small-signal equivalent circuit model; Step S2: Extracting external parasitic parameters based on the model in Step S1; Step S3: Extracting internal intrinsic parameters; In Step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters, wherein the external parasitic parameters are not affected by the applied bias voltage, including the parasitic capacitance C between metal electrodes. pg C pd and C pg External parasitic inductance L g L d and L s and external parasitic resistance R g R d and R s The intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R. gs Gate-drain resistance R gd Drain-source output conductance G ds Capacitance C between each port gs C gd C ds ; transconductance g m Delay parameter τ.

A semiconductor device includes a resistance element, a main transistor, a sub-transistor, and a two-dimensional electron gas. The main transistor may include a main channel layer, a barrier layer having a different energy band gap from the main channel layer and a main gate electrode on the barrier layer. Main source and main drain electrodes are located on opposite sides of the main gate electrode and are connected to the main channel layer. The sub-transistor may include a subchannel layer located apart from the main channel layer, a sub-gate electrode connected to the main source electrode, sub-source and sub-drain electrodes on opposite sides of the sub-gate electrode on the subchannel layer and electrically connected to the main gate electrode. The resistance element electrically interconnects the main gate electrode and the sub-source electrode or the main source electrode and the sub-gate electrode or a combination thereof.

An amplifier circuit includes an amplifier and a bias circuit. The bias circuit includes a bias transistor having a base terminal and a collector terminal, a transistor having a gate terminal, a source terminal, and a drain terminal, a transistor having a gate terminal, a source terminal, and a drain terminal, resistors, and a current source. The source terminals are connected to a power source. One end portion of the resistor is connected to the base terminal, the other end portion of the resistor is connected to the drain terminal, one end portion of the resistor is connected to the other end portion of the resistor, the other end portion of the resistor is connected to the bias output terminal, and the bias circuit further includes a feedback circuit that controls the electric potential of the base terminal based on the electric potential of the collector terminal.

A power converter includes an inductor configured to be coupled with a direct current voltage source. The power converter includes a first switching device coupled with the inductor and a second switching device coupled with the inductor. The first switching device and the second switching device are arranged in parallel. The first switching device and the second switching device have a similar drain resistance.