31 results about "Drain resistance" patented technology

The invention discloses a barrier GaN heterojunction transistor with low source-drain resistance and high Al component and a preparation method thereof, the transistor structurally comprises a substrate, a composite buffer layer, a channel layer, an isolation layer, a barrier layer and a cap layer which are sequentially arranged from bottom to top, source and drain electrodes are arranged at two ends of the surface of the cap layer, and a gate electrode is arranged between the source and drain electrodes. Etching is carried out on a partial region below the source and drain electrodes to form a nano groove array structure, inclined-angle ion implantation activation is carried out, N-type heavy doping is formed near a nano groove, and metal is filled in the nano groove to form the source and drain electrodes. Source and drain electrode metal of the structure is in direct contact with 2DEG, and forms ohmic contact after being annealed together with an N-type heavily doped region, so that the contact resistance is reduced. According to the method, the problem that the resistance value of a source-drain electrode contact resistor prepared by a conventional method of a high-Al-component barrier GaN heterojunction material is large is solved, the output current of a GaN heterojunction high-electron-mobility transistor device is increased, and the preparation process is simple, easy to implement and outstanding in effect.

The invention relates to the technical field of electronic circuits, and discloses a control circuit of a battery charging temperature protection chip, the control circuit comprises a plurality of MOS tubes, a plurality of resistors, a trigger, a capacitor and a connector, the source electrode of the MOS tube Q1 in the plurality of MOS tubes is connected with the drain electrode of the MOS tube Q3 and one end of the resistor R4, and the drain electrode is connected with the third pin of the trigger U1 and one end of the resistor R14; the grid electrode of the MOS tube Q2 is connected with the grid electrode of the MOS tube Q3 and the drain electrode of the MOS tube Q7, the source electrode is connected with the source electrode of the MOS tube Q3, one end of the capacitor C1 and one end of the resistor R13, and the drain electrode is connected with one end of the resistor R3; a first pin of the trigger U1 is connected with one end of a resistor R6, a second pin is connected with a sixth pin, a fourth pin and a resistor R3, and the other end of the resistor R6 is connected with a power supply; the source electrode of the MOS tube Q7 is connected with the P1 end of the connector; and the other ends of the resistor R4, the resistor R13, the resistor R14 and the capacitor C1 are grounded.

The utility model relates to a near-infrared communication circuit under power failure. The near-infrared communication circuit comprises a communication circuit and a power supply control circuit, the communication circuit comprises triodes QI2 and QI3, resistors RI1, RI2, RI3, RI4 and RI5, an infrared receiving tube DI2 and an infrared transmitting tube DI1; one end of the resistor RI6 is connected with a driving power supply VCC, and the other end of the resistor RI6 and one end of the resistor RI7 are used for being connected with a control pin InfaredPowerControl of a power supply; the other end of the resistor RI7 is connected with a drain resistor of the MOS tube QI1; the source electrode S of the MOS tube QI1 is connected with a power supply VCC, and the grid electrode D of the MOS tube QI1 outputs voltage VIND; the power supply control circuit comprises resistors RI6 and RI7 and a P-channel MOS (Metal Oxide Semiconductor) tube QI1; the negative electrode of the infrared receiving tube DI2 and the collector electrodes of the triodes QI2 and QI3 are connected to a driving voltage VIND, and the positive electrode of the infrared receiving tube DI2 is connected to the base electrode of the triode QI2 and connected to one end of the resistor RI5; the device is reasonable in design, compact in structure and convenient to use.

The invention relates to a high-power-supply-rejection-ratio low-dropout linear voltage regulator based on gate capacitance offset. The high-power-supply-rejection-ratio low-dropout linear voltage regulator comprises an error amplifier, a power tube MP, feedback networks R1 and R2, a load capacitor CL, a frequency compensation capacitor CM and a gate capacitance offset circuit. The output end of the error amplifier, the output end of the grid capacitance offset circuit and the grid of the power tube MP are connected with one end of the frequency compensation capacitor CM; the other end of the frequency compensation capacitor CM, the drain electrode of the power tube MP, one end of the resistor R1 and one end of the load capacitor CL are connected with a VOUT end; the source electrode of the power tube MP is connected with the VIN end; the other end of the load capacitor CL and one end of the resistor R2 are connected with a grounding end GND; the other end of the resistor R1 and the other end of the resistor R2 are connected with the in-phase input end VFB of the error amplifier. The gate capacitance offset circuit is introduced to the output of the error amplifier, so that the equivalent capacitance of the node is changed, the gain from input to output is reduced, and the power supply suppression capability is improved.

The utility model relates to the technical field of welding equipment detection, in particular to a welding table point inspection tester circuit, a welding table point inspection tester and a welding table. The utility model relates to a welding station spot inspection tester circuit, which is characterized by comprising a temperature detection circuit, a drain voltage detection circuit, a leakage resistance detection circuit, a multi-channel switching module, a display module and a central control unit, and the central control unit is used for receiving test data from the temperature detection circuit, the drain voltage detection circuit and the drain resistance detection circuit, judging the performance of the soldering station according to the test data, outputting a corresponding signal to control the multi-channel switching module to perform test switching, and outputting and displaying a detection result through the display module. According to the scheme, by integrating multiple functions, comprehensive monitoring of the performance of the welding table is achieved. Through efficient cooperation of all the modules, detection of the performance of the welding table is more efficient and accurate, and operation is easy and convenient.

A non-volatile memory device includes: a resistive switching layer; a gate on the resistive switching layer; a gate oxide layer between the resistive switching layer and the gate; and a source and a drain on the resistive switching layer and spaced apart from each other. The resistance value of the resistive switching layer changes based on the illuminance of light illuminating the resistive switching layer and remains at the changed resistance value.

The present invention relates to the technical field of transistor noise processing, and specifically relates to a method for calculating noise equivalence, a design method and device for a back-bias generation circuit. The method includes: using a noise current source and a noise voltage source to simulate and generate the noise of a MOS device; equivalently calculating the thermal noise of the drain resistance of the MOS device and the channel thermal noise of the MOS device; equivalently calculating the front-gate flicker noise of the MOS device and the back-gate flicker noise of the MOS device; and performing superposition calculation to obtain the output noise of the MOS device. By analyzing the noise of the MOS device in the FDSOI process, the present invention introduces interference signals representing noise into an ideal MOS device by using a noise current source and a noise voltage source, realizes the simulation calculation of the thermal noise of the drain resistance, the channel thermal noise, the front-gate flicker noise and the back-gate flicker noise of the MOS device, and thus accurately obtains the noise power of the MOS device in the FDSOI process.

The application discloses a leakage current processing circuit, a pixel circuit, a display panel and a display device. The leakage current processing circuit comprises: a resistance unit, an input end of the resistance unit being coupled to a first source-drain electrode of a thin film transistor, and an output end of the resistance unit being coupled to a pixel electrode; and an operational amplifier unit, an input end of the operational amplifier unit being coupled to the resistance unit, and an output end of the operational amplifier unit being coupled to the output end of the resistance unit through a target capacitor. The operational amplifier unit converts a sampling voltage of a sampling resistor in the resistance unit into a first leakage voltage in response to the leakage current of the resistance unit, inverses the first leakage voltage to obtain a second leakage voltage, and outputs the second leakage voltage to the target capacitor, so that the target capacitor offsets part of a pixel electrode voltage output from the output end of the resistance unit to the pixel electrode. In this way, the pixel voltage input to the pixel electrode is reduced, and the effect of improving the leakage of the thin film transistor is achieved.

A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source / drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source / drain regions, thereby forming a nanosheet transistor device.

The utility model relates to the technical field of power supply control circuits, in particular to a power supply switch control circuit based on an FPGA (Field Programmable Gate Array), which comprises NMOSD1 and D5, a PMOS (P-channel Metal Oxide Semiconductor) D2, switching diodes D3 and D4, a resettable key switch SW1, an FPGA unit U1, resistors R1-R7 and an FPGA, and a battery output power supply VCC IN is connected with a source electrode of the PMOS D2, a first end of a resistor R3, a first end of a resistor R4 and a first end of a resistor R5; the system power supply VCC OUT is connected with the drain electrode of the PMOS D2 and the first end of the resistor R1. Compared with the prior art, the power switch control circuit has the advantages that the power switch control circuit based on the FPGA is adopted, so that the portable equipment can keep extremely low standby power consumption in a power-off state, and the cruising ability of a battery is remarkably improved; the power switch control circuit is realized by using the existing key FPGA unit in the equipment, and compared with the traditional power control scheme, the power switch control circuit has the advantages that the use of part of control devices is reduced, so that the cost is reduced.

The present invention provides a method for manufacturing a display device, which reduces the source / drain resistance and realizes a TFT having stable Vd-Id characteristics in a display device having a TFT composed of an oxide semiconductor. A display device having a plurality of pixels each including a thin film transistor (TFT) composed of an oxide semiconductor (105), a channel is formed in the oxide semiconductor, a drain and a source are formed on both sides of the channel, an intermediate region is formed between the channel and the drain or between the channel and the source, a gate insulating film (106) is formed over the channel and the intermediate region of the oxide semiconductor, an alumina film (107) is formed over the gate insulating film, a gate electrode (109) is formed over the channel and over the alumina film, sidewall spacers (108) are formed on both sides of the gate electrode, and an interlayer insulating film (110) is formed so as to cover the gate electrode, the sidewall spacers, the source, and the drain.

The invention discloses a method and a system for measuring the under-gate electron mobility of a high-electron-mobility transistor, and mainly relates to the technical field of integrated circuit engineering. Comprising the following steps: testing gate-source currents corresponding to different gate-source voltages to obtain a first relational graph; based on the first relation graph, performing linear fitting to obtain gate-source resistance; testing gate-drain currents corresponding to different gate-drain voltages to obtain a second relational graph; based on the second relation graph, performing linear fitting to obtain gate-drain resistance; calculating the total resistance of the channel; and calculating the under-gate electron mobility. The method has the beneficial effects that the interference of parasitic resistance and contact resistance on migration rate extraction is effectively eliminated, and the calculation accuracy is improved.

Embodiments of the present application provide a display substrate, a method for manufacturing the same, a display panel, and a display device. The display substrate includes a base, a source / drain electrode disposed on one side of the base, a resistance compensation structure, and a pin. The resistance compensation structure is disposed on a side of the source / drain electrode away from the base. The pin is located in a binding region. One end of the resistance compensation structure is electrically connected to the source / drain electrode, and the other end is electrically connected to the pin. The resistance of the resistance compensation structure is greater than the resistance of the metal traces of the display substrate. Embodiments of the present application utilize a resistance compensation structure to replace a portion of the low-impedance metal traces in related art. This reduces the length of the metal trace between the pin and the source / drain electrode while meeting the resistance requirements for brightness uniformity at each display position within the display panel. This reduces the space occupied by the metal trace on the display substrate, reduces the space surrounded by the metal trace in the border region of the display substrate, and thereby reduces the size of the display substrate border, achieving a narrow border.

The present application belongs to the technical field of power integrated circuit, and particularly relates to a method for establishing and simulating a lateral high-voltage device equivalent circuit model. The circuit model comprises: a field effect transistor; a drain resistance, one end of which is connected to the drain of the field effect transistor and the second end of which is used as the drain of a high-voltage device; a source resistance, one end of which is connected to the source of the field effect transistor and the second end of which is used as the source of a high-voltage transistor; a body diode, which is connected in series with a diode cathode through a parallel network of a cathode resistance and an inductor, the anode of which is connected to the source of the high-voltage transistor, and the other end of the cathode resistance is connected to the drain of the high-voltage device; a first current source, one end of which is connected to the drain of the high-voltage device and the other end of which is connected to the source of the high-voltage device; and a simulation model, which uses a voltage control resistance value relationship to correct the resistance value of an external resistance. Compared with a traditional model, the resistance expression of the present application has a clear physical meaning, effectively improves the simulation accuracy of the lateral high-voltage device model, and has better convergence.

The utility model belongs to the technical field of control circuits, and discloses a delay turn-off control circuit, which comprises a resistor R2, one end of the resistor R2 is connected with a port DC + and one end of a resistor R3, the other end of the resistor R2 is connected with one end of a resistor R6, one end of a resistor R1 and a grid electrode of a switch tube Q1, the other end of the resistor R6 is connected with a port PSON, and the other end of the switch tube Q1 is connected with the port PSON. The other end of the resistor R3 is connected with one end of the resistor R4 and the drain electrode of the switch tube Q1, the other end of the resistor R4 is connected with one end of the resistor R5, one end of the capacitor C1 and the grid electrode of the switch tube Q2, the drain electrode of the switch tube Q2 is connected with a port CONTROL, and the other end of the resistor R1, the source electrode of the switch tube Q1, the other end of the resistor R5, the other end of the capacitor C1 and the source electrode of the switch tube Q2 are connected with a port AGND. The beneficial effects of the utility model are that: can delay the turn-off of the signal, provide enough time for the system to store data, satisfy the application of the system.

The invention provides a switching device overcurrent protection circuit and a transistor. The switching device overcurrent protection circuit comprises a target switching device and a resistance value self-adjusting circuit, the resistance value self-adjusting circuit is connected with a potential sampling point, and the potential sampling point comprises a source electrode of a target switching device or a drain electrode of the target switching device; the resistance value self-adjusting circuit is used for collecting the potential at the potential sampling point and adjusting the resistance value of the resistance value self-adjusting circuit according to the collected potential, so that the overcurrent on the target switching device is reduced, and the overcurrent tolerance time of the target switching device is prolonged. The circuit can quickly respond to the current change of a target switching device, adjusts the current of the target switching device by adjusting the resistance value of a target loop where the target switching device is located, prolongs the large current tolerance time of the target switching device while reducing the peak current of the switching device, and improves the switching efficiency. And enough time is reserved for an external control circuit to trigger a gate turn-off signal of a target switching device.

The application relates to a high-power-supply-rejection low-voltage-difference linear voltage stabilizer based on gate capacitance offset, which comprises an error amplifier, a power tube M P , a feedback network R1 and R2, a load capacitor C L , a frequency compensation capacitor C M and a gate capacitor offset circuit; the output end of the error amplifier, the output end of the gate capacitor offset circuit, the gate of the power tube M P and one end of the frequency compensation capacitor C M are connected; the other end of the frequency compensation capacitor C M , the drain of the power tube M P , one end of the resistor R1, one end of the load capacitor C L and the V OUT end are connected; the source of the power tube M P is connected to the V IN end; the other end of the load capacitor C L , one end of the resistor R2 and the ground end GND are connected; the other end of the resistor R1, the other end of the resistor R2 and the non-inverting input end V FB of the error amplifier are connected. The application changes the equivalent capacitance of a node by introducing a gate capacitor offset circuit at the output end of the error amplifier, reduces the input-to-output gain and improves the power supply rejection capability.

The application relates to a method for extracting key parameters of an enhancement-mode GaN device based on a depletion-mode GaN HEMT, belonging to the technical field of microelectronic research, and a same-size depletion-mode D-mode device is prepared beside an enhancement-mode E-mode device; since the size of the enhancement-mode E-mode device is completely same as that of the depletion-mode D-mode device, gate-source resistance and gate-drain resistance of the enhancement-mode device can be directly obtained through the depletion-mode device, and the key parameters of the enhancement-mode device can be quickly, conveniently and accurately extracted; since the depletion-mode device and the enhancement-mode device are adjacent, the gold-semiconductor contact resistance error value caused by uneven etching of P-GaN can be eliminated, and the accuracy of extraction of the key parameters of the device is improved; and the method for extracting the key parameters is realized based on a conventional structure and electrical test data, and does not need to introduce a complex structure and a destructive test.

A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

This invention discloses a parameter extraction method for the equivalent circuit model of a GaN HEMT device, comprising at least the following steps: Step S1: Modeling the GaN HEMT device as a small-signal equivalent circuit model; Step S2: Extracting external parasitic parameters based on the model in Step S1; Step S3: Extracting internal intrinsic parameters; In Step S1, the equivalent circuit model includes external parasitic parameters and internal intrinsic parameters, wherein the external parasitic parameters are not affected by the applied bias voltage, including the parasitic capacitance C between metal electrodes. pg C pd and C pg External parasitic inductance L g L d and L s and external parasitic resistance R g R d and R s The intrinsic parameters are affected by the channel structure and bias conditions during device operation, including the channel resistance R. gs Gate-drain resistance R gd Drain-source output conductance G ds Capacitance C between each port gs C gd C ds ; transconductance g m Delay parameter τ.

The invention provides a method and a structure for measuring upper source / drain resistance, which are applied to a vertical field effect transistor, the vertical field effect transistor comprises an upper source / drain region, and the method mainly comprises the following steps: leading out a first end, a second end and a third end from the upper source / drain region through contact holes; the first end, the second end and the third end are connected with an excitation end and / or a measurement end, and the excitation end is used for driving excitation current to flow between any two ends of the first end, the second end and the third end; the measuring end is used for measuring a voltage value between any two ends of the first end, the second end and the third end; obtaining a current value and a voltage value of the excitation current; and obtaining source-drain parasitic resistance of the upper source / drain region according to the current value and the voltage value. Three measuring ends are led out from the upper source / drain region, under the condition that the channel is closed, the resistance value of the source / drain parasitic resistor of the upper source / drain region is obtained by obtaining the current value and the voltage value of the excitation current, the number of the measuring ends and the layout area are saved, and the measuring efficiency is improved.

A semiconductor device includes a resistance element, a main transistor, a sub-transistor, and a two-dimensional electron gas. The main transistor may include a main channel layer, a barrier layer having a different energy band gap from the main channel layer and a main gate electrode on the barrier layer. Main source and main drain electrodes are located on opposite sides of the main gate electrode and are connected to the main channel layer. The sub-transistor may include a subchannel layer located apart from the main channel layer, a sub-gate electrode connected to the main source electrode, sub-source and sub-drain electrodes on opposite sides of the sub-gate electrode on the subchannel layer and electrically connected to the main gate electrode. The resistance element electrically interconnects the main gate electrode and the sub-source electrode or the main source electrode and the sub-gate electrode or a combination thereof.

The invention discloses an MOS attenuator based on a transistor parasitic capacitance compensation phase and a control method. The attenuator comprises a digital logic module, a grid bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, a radio frequency attenuation module and a detection feedback loop module. The method comprises the following steps: controlling the radio frequency attenuation module to generate attenuation and compensating a phase error of the radio frequency attenuation module in an attenuation state; performing feedback gate bias voltage regulation processing on the compensated radio frequency attenuation module through an off-chip differential signal; and controlling the additional phase shift of the adjusted radio frequency attenuation module in the attenuation state, and carrying out numerical control attenuation processing on the radio frequency signal of the input end. According to the invention, the increase degree of additional phase shift can be reduced, and the influence of the change of the process corner on the source-drain resistance when the MOS transistor is in the resistance region can be reduced. The MOS attenuator based on the transistor parasitic capacitance compensation phase and the control method can be widely applied to the technical field of CMOS transceiver gain control.

MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.

The application provides a method for growing multiple layers of source drain epitaxial silicon in an FDSOI process, forming a buried oxide layer on the substrate, and then forming an SOI layer on the buried oxide layer; forming a gate on the SOI layer, wherein a source drain region is provided on two sides of the gate; forming an undoped epitaxial layer on the SOI layer of the source drain region; forming a first doped epitaxial layer on the undoped epitaxial layer; forming a second doped epitaxial layer on the first doped epitaxial layer; and cleaning the substrate with deionized water. In the present application, the epitaxial silicon is changed from a single layer structure to a multilayer structure, wherein undoped epitaxial silicon can effectively prevent ion diffusion, and middle-highly doped epitaxial silicon and highly doped epitaxial silicon can significantly reduce source drain resistance and improve device performance.

A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source / drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source / drain regions, thereby forming a nanosheet transistor device.

An amplifier circuit includes an amplifier and a bias circuit. The bias circuit includes a bias transistor having a base terminal and a collector terminal, a transistor having a gate terminal, a source terminal, and a drain terminal, a transistor having a gate terminal, a source terminal, and a drain terminal, resistors, and a current source. The source terminals are connected to a power source. One end portion of the resistor is connected to the base terminal, the other end portion of the resistor is connected to the drain terminal, one end portion of the resistor is connected to the other end portion of the resistor, the other end portion of the resistor is connected to the bias output terminal, and the bias circuit further includes a feedback circuit that controls the electric potential of the base terminal based on the electric potential of the collector terminal.

The application discloses a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method, and the attenuator comprises a digital logic module, a gate bias and a capacitor switch module, a substrate capacitor switch module, a side edge capacitor module, a radio frequency attenuation module and a detection feedback loop module. The method comprises the following steps: controlling the radio frequency attenuation module to generate an attenuation amount and to compensate for the phase error of the radio frequency attenuation module in an attenuation state; performing feedback gate bias voltage adjustment processing on the compensated radio frequency attenuation module through an off-chip differential signal; and controlling the adjusted radio frequency attenuation module to have an additional phase shift in the attenuation state, and performing digital control attenuation processing on the radio frequency signal at the input end. The application can reduce the increase of the additional phase shift and reduce the influence of the change of the process angle on the source-drain resistance of the MOS transistor in the resistance region. The application, as a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method, can be widely applied to the field of CMOS transceiver gain control technology.

A power converter includes an inductor configured to be coupled with a direct current voltage source. The power converter includes a first switching device coupled with the inductor and a second switching device coupled with the inductor. The first switching device and the second switching device are arranged in parallel. The first switching device and the second switching device have a similar drain resistance.

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a broadband high-linearity low-noise amplifier, which comprises an RC negative feedback circuit from a signal input end to a signal output end; the self-adaptive active bias circuit is arranged from a signal input end to a signal output end, one end of a resistor R2 of the self-adaptive active bias circuit is connected with a drain electrode of a transistor T3, one end of a resistor R4 is connected with a source electrode of the transistor T3, the other end of the resistor R4 is grounded, a grid electrode of the transistor T3 is connected with one end of a capacitor C2, a positive electrode of a diode D1 and one end of a resistor R3, and the other end of the resistor R3 is grounded. The other end of the capacitor C2 is grounded, the other end of the resistor R3 is respectively connected with the other end of the resistor R2 and a radio frequency signal output end, the negative electrode of the diode D1 is connected with one end of a resistor R5, and the other end of the resistor R5 is connected with a radio frequency signal input end; and the cascode amplification circuit is arranged from the signal input end to the signal output end. According to the low-noise amplifier, the OIP3 of the circuit can be improved, and the aim of improving the linearity of the low-noise amplifier can be achieved.