33results about How to "Small subthreshold slope" patented technology

The invention provides a germanium-based NMOS (N-metal-oxide-semiconductor) device and a preparation method thereof, belonging to the technical field of ultra large scale integration (ULSI) circuit manufacturing. Two layers of insulation medium material are inserted among metal source and drain electrodes and a substrate of the germanium based-NMOS device, and the bottom layer is S medium material with high pinning coefficient, such as hafnium oxide, silicon nitride or hafnium silica, and the upper layer of medium material is delta EC medium material with low conduction band offset, such as titanium dioxide, gallium oxide or strontium titanium oxygen. According to the invention, the fermi energy level pinning effect can be weakened, the electronic potential barrier is reduced, and furtherthe performances of a germanium-based schottky NMOS device are improved; and compared with the traditional method in which a single layer of insulation medium material such as AL2O3 is adopted, the preparation method can be used for effectively reducing the schottky potential barrier and maintaining lower source and drain resistance, therefore, the performances of the device are improved to a large extent.

The invention provides a preparation method of a germanium-based Schottky N-type field effect transistor, belonging to the technical field of technical manufacturing of ultra large scale integrations (ULSI). In the preparation method, a high-k medium thin layer is formed among a germanium substrate, a metal source and a metal drain. On one hand, the thin layer can prevent an electron wave function in metal from introducing an MIGS (Metal Induction Gap Strip) interface state into a semiconductor forbidden band and can passivate a dangling bond of a germanium interface; and on the other hand, an insulating medium layer is very thin and electrons can freely pass through the insulating medium layer basically, so that the parasitic resistances of the source and the drain cannot be increased remarkably. By adopting the method, the Fermi level pinning effect can be wakened, the Fermi level is close to the conduction band position of germanium, and the electronic barrier is lowered, therefore, the electric current on-off ratio of the germanium-based Schottky transistor is increased, and the performance of an NMOS (Negative Channel Metal Oxide Semiconductor) device is improved.

The invention discloses a junction-modulated type tunneling field effect transistor and a manufacturing method of the junction-modulated type tunneling field effect transistor, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large scale integration (ULSI) circuits. According to the junction-modulated type tunneling field effect transistor, a PN junction provided by a highly-doped source region enclosed on three sides in a vertical channel region is utilized so that the channel region can be effectively used up, a surface channel energy band below a grid can be increased, a device can obtain a steeper energy band and a smaller tunneling barrier width compared with a traditional TFET when subjected to band-band tunneling, the effect of a steep tunnel junction doping density gradient is achieved equivalently, as a result, the subthreshold property of the traditional TFET is improved substantially, and breakover currents of the device are increased at the same time. According to the junction-modulated type tunneling field effect transistor and the manufacturing method of the junction-modulated type tunneling field effect transistor, under the condition that the junction-modulated type tunneling field effect transistor is compatible with an existing CMOS process, the bipolar breakover effect of the device is restrained effectively, parasitic tunneling currents at corners of a source junction with a small size also can be restrained, and the effect of steep source junction doping density can be achieved equivalently.

The invention discloses a method and corresponding device for restraining a tunneling transistor from leaking a current and a method for manufacturing the corresponding device and belongs to the field of field effect transistors and currents in a ULSI of a CMOS. According to the method for restraining the tunneling transistor from leaking the current, an insulating layer is inserted between a source zone and a body zone below a tunnel junction, an insulating layer is not inserted in the portion, between the source zone and a tunnel, of the tunnel junction, so that the source zone and a drain zone in a small-size TFET device are effectively prevented from being directly tunneled and leaking the current, and meanwhile the slope of a subthreshold value can be effectively improved. The method for manufacturing the corresponding device is compatible with the existing CMOS technology.

A semiconductor structure and a method for forming the same, wherein the forming method includes: forming a sidewall covering a channel region of a fin pillar and a sidewall of a top region; using the sidewall as a mask, forming on the surface of the sidewall of the bottom region a first conductive structure; after the first conductive structure is formed, the spacer is removed; after the spacer is removed, a gate structure is formed on top of the first conductive structure, and the gate structure is located in the fin pillar trench the surface of the channel region; after the gate structure is formed, a second conductive structure is formed on the top of the gate structure, and the second conductive structure is located on the surface of the top region of the fin column. The forming method can improve the integration degree of the formed semiconductor structure.

The invention relates to a high-dielectric gate dielectric material for flexible low-voltage driving organic thin film transistors and a preparation method thereof, comprising the following steps: 1) preparing a lanthanum oxide precursor solution; 2) preparing a lanthanum oxide dielectric layer film: combining step 1) After the obtained lanthanum oxide precursor solution is filtered, the lanthanum oxide precursor solution is spin-coated on the substrate to obtain a lanthanum oxide precursor film; 3) the samples obtained in step 2) are sequentially subjected to pre-annealing treatment, heat treatment and ozone activation treatment Finally, a lanthanum oxide dielectric layer is obtained, that is, a high dielectric gate dielectric material is obtained. The high-dielectric gate dielectric material lanthanum oxide dielectric layer of the present invention has a high dielectric constant and a wide energy band, which can effectively reduce the working voltage required by the device; and it is prepared by a solution method, and can form a dense Non-toxic thin film, simple process and low cost. The invention also provides a flexible low-voltage driving organic thin film transistor using the high-dielectric gate dielectric material as a dielectric layer and a preparation method thereof.

The invention provides a biosensor based on sSOI MOSFET and a preparation method of the biosensor. The preparation method comprises the following steps: 1) providing an sSOI substrate, wherein the thickness of top strain silicon of the sSOI substrate is 10nm-50nm; 2) manufacturing a device region; 3) forming an N+ source region, an N+ drain region and a strain channel region; 4) forming a dielectric layer on the surface of the sSOI substrate; 5) forming a metal contact opening hole and manufacturing a metal contact electrode; 6) manufacturing an electrode protective layer and exposing a grid sensing region; 7) manufacturing a back grid on the back of the body silicon substrate; and 8) performing surface activation modification on the surface of the grid sensing region. Through the adoption of the preparation method, the strain silicon is used as the channel, and a high signal to noise ratio is obtained since the migration rate of the channel material is increased through the strain technology; the channel is in a full exhaustion state along with the thinning of the channel material, the subthreshold slope of the corresponding device is reduced, and the high sensitivity is obtained; therefore, the biosensor provided by the invention can be used for detecting biomolecules with high sensitivity.

The invention relates to a bi-material railing nanowire tunneling field effect device and a manufacturing method thereof. According to the bi-material railing nanowire tunneling field effect device, a channel is arranged at the center, and a source region and a drain region are respectively arranged at two ends, and an oxide and a gate electrode are covered at the periphery of the channel in sequence. The manufacturing method comprises the steps: SF6 etching a silicon column on a silicon wafer by using a round silicon nitride hard mask; conducting high-temperature oxidation, corroding and reducing the size of the silicon column to be a set diameter value of 6nm-30nm with HF aqueous solution, and conducting high-temperature oxidation to form a silicon column coated by an oxidation layer with set thickness; completing the preparation of a bi-material railing structure by adopting deposition and photoetching technology; and injecting boron and phosphorus of 1*10<20>cm<-2> / 10keV and 5*10<18>cm<-2> / 10keV at 120-150 DEG C respectively, and annealing at 900 DEG C / 10s-1100 DEG C / 10s to prepare the source region and the drain region; completing preparation of a metal electrode by CMOS (Complementary Metal-Oxide-Semiconductor) process; and manufacturing the bi-material railing nanowire tunneling field effect device.

The invention discloses a nanowire transistor based on resonance tunneling. The nanowire transistor comprises an SOI substrate, a tunneling barrier structure, a source region, a drain region, nanowires, a grid electrode, a source electrode, a drain electrode, a grid electrode and an insulating dielectric layer. The tunneling barrier structure is located on the buried oxide layer of the SOI substrate. The source region, the drain region and the nanowire are formed by etching top silicon of the SOI substrate; the nanowire is positioned between the source region and the drain region; wherein thesource region, the drain region and the nanowire are not directly connected and are connected through a tunneling barrier structure, the insulating dielectric layer is formed on the surfaces of the source region, the drain region and the nanowire, the grid electrode is formed on the insulating dielectric layer above the nanowire, the source electrode is formed on the source region, the drain electrode is formed on the drain region, and the grid electrode is formed on the grid electrode. According to the nanowire transistor structure based on resonance tunneling and the preparation method of the nanowire transistor structure, the sub-threshold slope is reduced, and large conduction current and small source-drain contact resistance can be achieved.

The present invention provides a gate-all-around transistor and a preparation method thereof, the method comprising: 1) providing an SOI substrate with grooves formed in its insulating layer; 2) forming a semiconductor nanowire structure suspended and straddling the grooves; 3) ) rounding and thinning the semiconductor nanowire structure; 4) forming a fully enclosed gate dielectric layer on the surface of the semiconductor nanowire, and forming a gate electrode layer on the surface of the gate dielectric layer; 5) using the gate electrode layer as a mask to perform An ion implantation process to form a source region and a drain region; 6) removing the gate dielectric layer outside the gate electrode layer; 7) forming a source electrode and a drain electrode in the source region and the drain region. The invention adopts the gate electrode layer as a mask to carry out the self-alignment implantation of the source region and the drain region, which can effectively improve the process stability and implantation precision, and can effectively reduce the process cost. The invention does not need isotropic wet etching when preparing semiconductor nanowires, and can effectively avoid the generation of concave cavities.

The present invention provides a three-dimensional stacked gate-all-around transistor and a preparation method thereof. The method includes: 1) providing an SOI substrate with grooves formed in its insulating layer; Semiconductor nanowire structure; 3) Rounding and thinning the semiconductor nanowire structure; 4) Forming a fully enclosed gate dielectric layer and gate electrode layer on the surface of the semiconductor nanowire; 5) Using the gate electrode layer as a mask, ions Implanting to form a source region and a drain region; 6) removing the gate dielectric layer outside the gate electrode layer; 7) forming a source electrode and a drain electrode in the source region and the drain region. The invention adopts the gate electrode layer as a mask to carry out the self-alignment implantation of the source region and the drain region, which can effectively improve the process stability and implantation precision. The invention does not need isotropic wet etching when preparing semiconductor nanowires, and can effectively avoid the generation of concave cavities. The invention can effectively improve the integration degree of devices.

The invention provides a method for preparing a gate-all-around transistor, the method comprising: 1) providing an SOI substrate with a groove formed in its insulating layer; 2) forming a semiconductor nanowire structure suspended and straddling the groove; 3) Rounding and thinning the semiconductor nanowire structure; 4) forming an implantation barrier layer on the surface of the channel region, the implantation barrier layer reveals the preparation area of ​​the source region and the drain region; 5) performing an ion implantation process to form the source region and drain region; 6) forming a fully-enclosed gate dielectric layer and a gate electrode layer on the surface of the semiconductor nanowire, and patterning to form a gate structure; 7) forming a source electrode and a drain electrode. The gate-all-round transistor of the present invention is prepared by a gate-last process, which can effectively increase the selection range of gate materials, thereby realizing different device performance requirements. The invention does not need isotropic wet etching when preparing semiconductor nanowires, and can effectively avoid the generation of concave cavities.

The present invention provides a semiconductor device and a method for forming the same, wherein the method includes: forming a semiconductor substrate, the semiconductor substrate including a gate region and a first region and a second region respectively located on both sides of the gate region, There is an epitaxial layer in the semiconductor substrate in the first region, and the energy gap of the epitaxial layer is smaller than the energy gap of the semiconductor substrate; a first doped region is formed in the epitaxial layer in the first region, and the first There are first doping ions in the doping region; a gate structure is formed on the semiconductor substrate in the gate region; a second doping region is formed in the semiconductor substrate in the second region, and the second doping region There are second dopant ions in which the conductivity type of the second dopant ions is opposite to that of the first dopant ions. If the bandgap of the epitaxial layer is smaller than that of the semiconductor substrate, the barrier width on the contact surface between the first doped region and the channel region will be smaller. Therefore, the forming method can reduce the Formation of subthreshold slopes for semiconductor devices.

The present disclosure provides a tunneling device, which comprises: a substrate (1100); a channel region (1300) formed in the substrate, and a source region (1500) and a drain region (1400) formed on two sides of the channel region (1300); and a gate stack (1600) formed on the channel region (1300) and a first side wall (1910) and a second side wall (1920) formed on two sides of the gate stack (1600), wherein the gate stack (1600) comprises: a first gate dielectric layer (1631); at least a first gate electrode (1610) and a second gate electrode (1620) formed on the first gate dielectric layer (1631); a second gate dielectric layer (1632) formed between the first gate electrode (1610) and the first side wall (1910); and a third gate dielectric layer (1633) formed between the second gate electrode (1620) and the second side wall (1920).