31results about How to "Small subthreshold slope" patented technology

The invention provides a surrounding gate nanowire field effect transistor and a preparation method thereof. The preparation method comprises the following steps of S1, forming a first fin body isolated from a substrate on the substrate, wherein the first fin body consists of a first region, a second region and a third region which are connected in sequence in the length direction; S2, forming a nanowire structure in the second region of the first fin body; and S3, forming an interface oxide layer, a ferroelectric layer and a gate which are laminated around the exposed surface of the nanowirestructure in sequence, wherein the preparation method also comprises the following steps of forming a source/drain in the first region and the third region, wherein the source/drain is connected withthe two ends of the nanowire structure. By virtue of the preparation method, the gate control capability of the device is improved, electric leakage of the device is lowered, source/drain parasitic resistance of the device is lowered, and the sub threshold value slope of the device can be greatly lower than 60mV/dec.

The invention relates to a bi-material railing nanowire tunneling field effect device and a manufacturing method thereof. According to the bi-material railing nanowire tunneling field effect device, a channel is arranged at the center, and a source region and a drain region are respectively arranged at two ends, and an oxide and a gate electrode are covered at the periphery of the channel in sequence. The manufacturing method comprises the steps: SF6 etching a silicon column on a silicon wafer by using a round silicon nitride hard mask; conducting high-temperature oxidation, corroding and reducing the size of the silicon column to be a set diameter value of 6nm-30nm with HF aqueous solution, and conducting high-temperature oxidation to form a silicon column coated by an oxidation layer with set thickness; completing the preparation of a bi-material railing structure by adopting deposition and photoetching technology; and injecting boron and phosphorus of 1*10<20>cm<-2>/10keV and 5*10<18>cm<-2>/10keV at 120-150 DEG C respectively, and annealing at 900 DEG C/10s-1100 DEG C/10s to prepare the source region and the drain region; completing preparation of a metal electrode by CMOS (Complementary Metal-Oxide-Semiconductor) process; and manufacturing the bi-material railing nanowire tunneling field effect device.

The invention belongs to the field of semiconductor integrated circuits, and specifically relates to a tunneling field effect device for channel potential barrier height control. The center of the device is provided with a channel, two ends of the channel are provided with a source terminal and a drain terminal of different conductive types, a tunneling junction is formed between the source terminal and the channel, the channel is formed by the adoption of three or more than three potential barrier areas, the energy band of the potential barrier area at the middle section is higher than the energy bands of the channel close to the drain terminal and the source terminal, the device also comprises a gate oxide layer fully covering the channel, and the gate oxide layer is fully covered by a gate electrode. The portion of the channel of the device employs materials of different doping concentrations or types, and three sections or more sections of the potential barrier structures are formed in the channel. According to the simulation research result of the tunneling device structure for channel potential barrier height control, the off-state leakage current of the device can be effectively reduced, the sub-threshold slope is reduced, the short-channel effect and the DIBL effect are suppressed, the transconductance characteristic is good, and comprehensive optimization of the performance of the device is realized.

The invention discloses a nanowire transistor based on resonance tunneling. The nanowire transistor comprises an SOI substrate, a tunneling barrier structure, a source region, a drain region, nanowires, a grid electrode, a source electrode, a drain electrode, a grid electrode and an insulating dielectric layer. The tunneling barrier structure is located on the buried oxide layer of the SOI substrate. The source region, the drain region and the nanowire are formed by etching top silicon of the SOI substrate; the nanowire is positioned between the source region and the drain region; wherein thesource region, the drain region and the nanowire are not directly connected and are connected through a tunneling barrier structure, the insulating dielectric layer is formed on the surfaces of the source region, the drain region and the nanowire, the grid electrode is formed on the insulating dielectric layer above the nanowire, the source electrode is formed on the source region, the drain electrode is formed on the drain region, and the grid electrode is formed on the grid electrode. According to the nanowire transistor structure based on resonance tunneling and the preparation method of the nanowire transistor structure, the sub-threshold slope is reduced, and large conduction current and small source-drain contact resistance can be achieved.

The invention provides a multichannel gate-all-around transistor. The multichannel gate-all-around transistor comprises: a semiconductor substrate; an insulating layer which is provided with a groovewhich does not penetrate through the insulating layer; a semiconductor nanowire structure which is suspended in the air, stretches across the groove and comprises semiconductor bosses located on the two sides of the groove and a plurality of semiconductor nanowires connected to the bosses; a gate dielectric layer and a gate electrode layer which surround the semiconductor nanowires; a source region and a drain region which are formed at the end parts of the semiconductor nanowires, wherein the plurality of semiconductor nanowires between the semiconductor bosses form a multichannel channel region together; and a source electrode and a drain electrode. The width of the groove below the multichannel gate-all-around transistor is smaller than that of the semiconductor nanowires, so that an unnecessary overlapping region between the bottom gate and the source drain can be effectively avoided, the scattering of carriers in a channel is reduced, the parasitic capacitance of the source drainis reduced, and the high-frequency characteristic of the device is improved. The gate-all-around transistor is provided with a plurality of channels, the driving power of the transistor can be greatlyimproved, and the integration level of a device is improved.

A semiconductor structure and a forming method thereof are provided. The forming method comprises the following steps: forming a spacer covering the side walls of a channel region and a top region ofeach fin column; forming a first conductive structure on the side wall surface of each bottom region with the spacers as masks; removing the spacers after forming the first conductive structures; forming a gate structure on the top of each first conductive structure after removing the spacers, wherein the gate structures are located on the surfaces of the channel regions of the fin columns; and forming a second conductive structure on the top of each gate structure after forming the gate structures, wherein the second conductive structures are located on the surfaces of the top regions of thefin columns. The forming method can improve the integration degree of the formed semiconductor structure.

The invention provides a fin type field effect transistor and a preparation method thereof. The preparation method comprises the following steps of S1, forming a first fin body isolated from a substrate on the substrate, wherein the first fin body consists of a first region, a second region and a third region which are connected in sequence in the length direction; and S2, forming an interface oxide layer, a ferroelectric layer and a gate which are laminated around the exposed surface of the second region in sequence, wherein the preparation method also comprises the following steps of forminga source/drain in the first region and the third region, wherein the source/drain is connected with the two ends of the second region. By virtue of the preparation method, the gate control capabilityof the device is improved, electric leakage of the device is lowered, and the sub threshold value slope of the device can be greatly lower than 60mV/dec.

The invention provides a semiconductor device and a formation method thereof. The method comprises the steps of forming a semiconductor substrate, wherein the semiconductor substrate comprises a gateregion, a first region and a second region, the first region and the second region are respectively arranged at two sides of the gate region, an epitaxial layer is arranged in the semiconductor substrate at the first region, and the energy gap of the epitaxial layer is smaller than the energy gap of the semiconductor substrate; forming a first doping region in the epitaxial layer at the first region, wherein first doping ions are arranged in the first doping region; forming a gate structure on the semiconductor substrate at the gate region; and forming a second doping region in the semiconductor substrate at the second region, wherein second doping ions are arranged in the second doping region, and the conductive type of the second doping ions is opposite to the conductive type of the first doping ions. The bandgap of the epitaxial layer is smaller than the bandgap of the semiconductor substrate, the barrier width of a contact surface of the first doping region and a channel region isrelatively small, and thus, the subthreshold slope of the formed semiconductor device can be reduced.

The invention belongs to the technical field of microelectronic devices, and discloses a negative capacitance L-shaped gate tunneling field effect transistor and a preparation method thereof. The negative capacitance L-shaped gate tunneling field effect transistor comprises a buried oxide layer, a P-substrate, an N + type interlayer, a P + type source region, a gate oxide layer medium, a ferroelectric medium layer, a gate region and a drain region; the P + type source region and the N + type interlayer are located in the upper left portion of the P-substrate from top to bottom, the gate oxide layer medium is located in the right side of the N + type interlayer, the gate region is located on the gate oxide layer, the drain region is located on the right portion of the P-substrate, and the buried oxide layer is located below the P-substrate. A metal//Hf0.5Zr0.5O/HfO2/Si stacked structure is formed in the left side of the P + source region, so that the grid control capability is improved, the channel surface potential is increased, and the on-state current of the tunneling field effect transistor TFET is improved; and the N + interlayer and the P + source region are generated in the left side of the gate region, the tunneling area is increased, and line tunneling is expected to be formed.