33results about How to "Small subthreshold slope" patented technology

The invention provides a germanium-based NMOS (N-metal-oxide-semiconductor) device and a preparation method thereof, belonging to the technical field of ultra large scale integration (ULSI) circuit manufacturing. Two layers of insulation medium material are inserted among metal source and drain electrodes and a substrate of the germanium based-NMOS device, and the bottom layer is S medium material with high pinning coefficient, such as hafnium oxide, silicon nitride or hafnium silica, and the upper layer of medium material is delta EC medium material with low conduction band offset, such as titanium dioxide, gallium oxide or strontium titanium oxygen. According to the invention, the fermi energy level pinning effect can be weakened, the electronic potential barrier is reduced, and furtherthe performances of a germanium-based schottky NMOS device are improved; and compared with the traditional method in which a single layer of insulation medium material such as AL2O3 is adopted, the preparation method can be used for effectively reducing the schottky potential barrier and maintaining lower source and drain resistance, therefore, the performances of the device are improved to a large extent.

The invention discloses a junction-modulated type tunneling field effect transistor and a manufacturing method of the junction-modulated type tunneling field effect transistor, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large scale integration (ULSI) circuits. According to the junction-modulated type tunneling field effect transistor, a PN junction provided by a highly-doped source region enclosed on three sides in a vertical channel region is utilized so that the channel region can be effectively used up, a surface channel energy band below a grid can be increased, a device can obtain a steeper energy band and a smaller tunneling barrier width compared with a traditional TFET when subjected to band-band tunneling, the effect of a steep tunnel junction doping density gradient is achieved equivalently, as a result, the subthreshold property of the traditional TFET is improved substantially, and breakover currents of the device are increased at the same time. According to the junction-modulated type tunneling field effect transistor and the manufacturing method of the junction-modulated type tunneling field effect transistor, under the condition that the junction-modulated type tunneling field effect transistor is compatible with an existing CMOS process, the bipolar breakover effect of the device is restrained effectively, parasitic tunneling currents at corners of a source junction with a small size also can be restrained, and the effect of steep source junction doping density can be achieved equivalently.

A semiconductor structure and a method for forming the same, wherein the forming method includes: forming a sidewall covering a channel region of a fin pillar and a sidewall of a top region; using the sidewall as a mask, forming on the surface of the sidewall of the bottom region a first conductive structure; after the first conductive structure is formed, the spacer is removed; after the spacer is removed, a gate structure is formed on top of the first conductive structure, and the gate structure is located in the fin pillar trench the surface of the channel region; after the gate structure is formed, a second conductive structure is formed on the top of the gate structure, and the second conductive structure is located on the surface of the top region of the fin column. The forming method can improve the integration degree of the formed semiconductor structure.

The invention relates to a bi-material railing nanowire tunneling field effect device and a manufacturing method thereof. According to the bi-material railing nanowire tunneling field effect device, a channel is arranged at the center, and a source region and a drain region are respectively arranged at two ends, and an oxide and a gate electrode are covered at the periphery of the channel in sequence. The manufacturing method comprises the steps: SF6 etching a silicon column on a silicon wafer by using a round silicon nitride hard mask; conducting high-temperature oxidation, corroding and reducing the size of the silicon column to be a set diameter value of 6nm-30nm with HF aqueous solution, and conducting high-temperature oxidation to form a silicon column coated by an oxidation layer with set thickness; completing the preparation of a bi-material railing structure by adopting deposition and photoetching technology; and injecting boron and phosphorus of 1*10<20>cm<-2> / 10keV and 5*10<18>cm<-2> / 10keV at 120-150 DEG C respectively, and annealing at 900 DEG C / 10s-1100 DEG C / 10s to prepare the source region and the drain region; completing preparation of a metal electrode by CMOS (Complementary Metal-Oxide-Semiconductor) process; and manufacturing the bi-material railing nanowire tunneling field effect device.

The present invention provides a three-dimensional stacked gate-all-around transistor and a preparation method thereof. The method includes: 1) providing an SOI substrate with grooves formed in its insulating layer; Semiconductor nanowire structure; 3) Rounding and thinning the semiconductor nanowire structure; 4) Forming a fully enclosed gate dielectric layer and gate electrode layer on the surface of the semiconductor nanowire; 5) Using the gate electrode layer as a mask, ions Implanting to form a source region and a drain region; 6) removing the gate dielectric layer outside the gate electrode layer; 7) forming a source electrode and a drain electrode in the source region and the drain region. The invention adopts the gate electrode layer as a mask to carry out the self-alignment implantation of the source region and the drain region, which can effectively improve the process stability and implantation precision. The invention does not need isotropic wet etching when preparing semiconductor nanowires, and can effectively avoid the generation of concave cavities. The invention can effectively improve the integration degree of devices.