30results about How to "Suppression of bipolar effects" patented technology

The invention provides a tunneling field effect transistor and a preparation method thereof. The preparation method at least comprises the following steps that an SOI substrate provided with top layer silicon, an oxygen buried layer and bottom layer silicon is provided, and ion injection is conducted on the two sides of the top layer silicon to form a source electrode and a drain electrode respectively; an intrinsic silicon layer, and a grid medium layer and a grid layer are sequentially formed on the surface of the SOI substrate from bottom to top; a stacking structure is formed by etching the intrinsic silicon layer, the grid medium layer and the grid layer through the photoetching and etching technologies, the stacking structure is partially overlapped with the source electrode and is preset distance away from the drain electrode in the horizontal direction. According to the tunneling field effect transistor and the preparation method of the tunneling field effect transistor, the stacking structure is overlapped with the source electrode so that the tunneling area can be increased, and further a driving current is increased. In addition, the stacking structure is preset distance away from the drain electrode in the horizontal direction, and the bipolar effect in the tunneling field effect transistor can be suppressed through the preset distance, and a subthreshold current is reduced.

The invention relates to a PNIN/NPIP type SSOI TFET with abrupt tunneling junctions and a preparation method thereof. The preparation method comprises the steps that an SSOI substrate is prepared; shallow trench isolation is formed; a drain region pattern is formed through photoetching, and adhesive ions are injected so that a drain region is formed; a source region trench is formed through dry etching; the ions are injected in the side wall of the source region trench at a certain inclined angle by adopting an ion injection technology, Si material is deposited in the source region trench, and in-situ doping is performed so that a source region is formed; a gate dielectric layer and a front gate layer are formed on the upper surface of the substrate, a front gate is formed through etching, a back gate layer is formed on the lower surface of the substrate, and a back gate is formed through etching; and a lead-wire window is photoetched, metal is deposited and a lead-wire is photoetched so that source/drain and front/back gate lead-wires are formed. Drive current of the TFET can be effectively enhanced and subthreshold slope of the TFET can be reduced.

The invention discloses a self-alignment preparation method for a self-alignment gate-drain negative overlapping region of a tunneling field effect transistor, and belongs to the field of field effecttransistor logic devices and circuits in a CMOS ultra-large integrated circuit (ULSI). According to the method, asymmetric side wall structures are designed on the two sides of a tunneling transistorgate, the side, close to a source end, of the gate is a thin side wall, and the side, close to a drain end, of the gate is a thick side wall. According to the invention, by reasonably utilizing the thin side wall and the thick side wall in the standard CMOS process, the thin side wall at the source end is used as a hard mask for transistor source region injection, and the thick side wall at the drain end is used as a hard mask for transistor drain region injection, so that special materials and special processes are not introduced, the bipolar effect of a tunneling field effect transistor (TFET) is inhibited, the fluctuation characteristic of the device is optimized, it can be guaranteed that the TFET can be mixed and integrated with a standard CMOS device, and complex and diversified circuit functions are achieved.

The invention relates to an ultra-thin-body-silicon-on-insulator (UTB-SOI) tunneling field-effect transistor with an abrupt tunneling junction and a preparation method. The preparation method comprises: selecting a UTB-SOI substrate; forming a shallow trench isolation unit; carrying out photoetching to form a drain region graph and carrying out adhesive ion implantation to form a drain region; carrying out dry etching to form a source region trench; carrying out silicon material deposition in the source region trench and carrying out in-situ doping to form a source region; forming a gate dielectric layer and a front gate layer, and carrying out etching to form a front gate; and carrying out lead window photoetching, metal deposition, and lead photoetching to form source/drain and front gate leads. According to the invention, ion implantation is carried out on the drain region by using an ion implantation process, so that an intrinsic region/drain region junction with the gradually-changed doping concentration gradient can be formed well and the bipolar effect of the tunneling field effect transistor can be effectively inhibited; with the technique and preparation of trench etching and selective epitaxy deposition and filling at the source region, the tunnel junction area can be limited precisely; and on the basis of in-situ doping, the tunnel junction with the steep doping concentration gradient can be formed well and the driving current of the device can be effectively improved and the sub-threshold slope can be reduced.

The invention relates to an insulation layer upwards-expanded strained germanium tunneling field effect transistor (TFET) with an abrupt tunneling junction and a preparation method. The preparation method comprises the following steps of: preparing an insulation layer upwards-expanded strained germanium substrate; forming shallow groove isolation by an etching process; forming a drain region pattern on the upper surface of the substrate by the etching process, and forming a drain region on the substrate by a glued ion implantation technology; forming a source region groove on the substrate by a dry etching process; depositing a germanium material in the source region groove, and simultaneously carrying out in-situ doping to form a source region; forming a grid interface layer, a grid dielectric layer and a front grid layer on the upper surface of the substrate, and forming a front grid by the dry etching process; growing a back grid layer on the lower surface of the substrate, and forming a back grid by the dry etching process; and carrying out photoetching of a lead window, metal deposition and lead photoetching, forming metal leads of the source region, the drain region, the front grid and the back grid, and finally forming the insulation layer upwards-expanded strained TFET with the abrupt tunneling junction.