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Pnin/npip type utb-soi TFET with abrupt tunneling junction and preparation method

A UTB-SOITFET, UTB-SOI technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of sub-threshold slope theoretical value degradation, small drive current, low leakage current, etc., to suppress bipolar effect, increase device drive current, and reduce process difficulty

Inactive Publication Date: 2017-12-19
XIAN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to overcome the problems of low driving current of existing silicon-based TFET devices and the degradation of subthreshold slope relative to the theoretical value, the present invention proposes a PNIN / NPIP type UTB-SOI TFET with abrupt tunneling junction and its preparation method, which can effectively improve the TFET device drive current and reduces subthreshold slope while maintaining low leakage current

Method used

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  • Pnin/npip type utb-soi TFET with abrupt tunneling junction and preparation method
  • Pnin/npip type utb-soi TFET with abrupt tunneling junction and preparation method
  • Pnin/npip type utb-soi TFET with abrupt tunneling junction and preparation method

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Embodiment 1

[0025] See figure 1 , figure 1 It is a flow chart of a preparation method of a PNIN / NPIP type UTB-SOITFET with a sudden tunnel junction according to an embodiment of the present invention, and the preparation method includes the following steps:

[0026] (a) Select Ultra-Thin-Body-Silicon-On-Insulator (UTB-SOI for short) substrate;

[0027] (b) Form shallow trench isolation on UTB-SOI substrate;

[0028] (c) Photolithographically form a drain region pattern at a specified position on the UTB-SOT substrate, and form a drain region by using an ion implantation process with glue;

[0029] (d) using a dry etching process to form a trench in the source region on the UTB-SOI substrate at a position other than the designated position;

[0030] (e) using an inclined ion implantation process to implant ions into the sidewall of the source trench near the drain region to form a thin-layer doped region, and the doping type of the thin-layer doped region is different from the doping ...

Embodiment 2

[0071] See Figure 2a-2i , Figure 2a-Figure 2i It is a schematic diagram of the preparation method of a PNIN / NPIP type UTB-SOI TFET with an abrupt tunneling junction according to an embodiment of the present invention, taking the preparation of a PNIN type UTB-SOI TFET with an abrupt tunneling junction with a channel length of 45 nm as an example for detailed description Instructions, the specific steps are as follows:

[0072] 1. Select UTB-SOI substrate

[0073] Such as Figure 2a , the crystal orientation of the UTB-SOI substrate 101 may be (100) or (110) or (111), without any limitation here, and the doping type of the UTB-SOI substrate 101 may be N type, It can also be P-type, with a doping concentration of 10 14 ~10 17 cm -3 , the thickness of the top layer Si is, for example, 10-20 nm.

[0074] 2. Shallow trench isolation formation, such as Figure 2b shown.

[0075] 2.1 Form a first protective layer on the UTB-SOI substrate.

[0076] First, two layers of mat...

Embodiment 3

[0129] See image 3 , image 3 It is a structural schematic diagram of a PNIN / NPIP type UTB-SOITFET with an abrupt tunneling junction according to an embodiment of the present invention. The PNIN / NPIP UTB-SOITFET with an abrupt tunneling junction of the present invention includes an ultra-thin top silicon layer, a buried oxide Layer, underlying silicon layer, gate dielectric layer, front gate, back gate, highly doped source region, low doped drain region and N-type / P-type thin layer.

[0130] Specifically, the thickness of the ultra-thin fully depleted top silicon layer is preferably 10-20 nm, and the doping concentration is less than 10 17 cm -3 .

[0131] Specifically, the material of the gate dielectric layer can be selected from hafnium-based materials (a type of high dielectric constant material), such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZrO or a combination thereof, other high dielectric constant materials such as Al 2 o 3 , La 2 o 3 , ZrO 2 Or one or a c...

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Abstract

The invention relates to a PNIN / NPIP-type UTB-SOI TFET with an abruptly-changed tunnel junction and a preparation method thereof. The method comprises steps of: selecting a UTB-SOI substrate; forming shallow trench isolation in the substrate; forming a drain region in the substrate by using glue ion implantation technology; forming a source region trench in the substrate by using dry etching technology; implanting ions into the sidewall of the source region trench by using inclined ion implantation technology in order to form a thin layer doped zone; depositing intrinsic silicon material in the source region trench and simultaneously performing in-situ doping in order to form a source region; forming a gate dielectric layer and a front gate layer on the top silicon face of the substrate and forming a front gate by using dry etching technology; and photoetching a lead window, depositing metal, photoetching a lead, forming a source region, a drain region, and a front gate metal lead in order to finally form the PNIN / NPIP-type UTB-SOI TFET. The PNIN / NPIP-type UTB-SOI TFET with the abruptly-changed tunnel junction is effectively increased in the driving current and decreased in subthreshold slope, and maintains low leakage current.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a PNIN / NPIP type UTB-SOIT FET with an abrupt tunneling junction and a preparation method. Background technique [0002] The development of Integrated Circuit (IC) technology follows the "Moore's Law" and has entered the nanometer scale. Challenges from short channel effects, parasitic effects, and quantum tunneling make it increasingly difficult for traditional microelectronic device technology to meet The requirements for the continuous development of IC technology, especially the increasingly serious power consumption problem, have become the biggest bottleneck in the continuation of "Moore's Law". [0003] The tunneling field effect transistor (Tunneling Field Effect Transistor, referred to as TFET) adopts the physical mechanism of band-band tunneling, so that its sub-threshold swing breaks through the limitation of the traditional MOSFET ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/06H01L29/423
CPCH01L29/0684H01L29/42312H01L29/66409H01L29/78
Inventor 李妤晨刘树林童军张岩张超徐大庆岳改丽杨波刘宁庄秦学斌
Owner XIAN UNIV OF SCI & TECH
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