Tunneling field effect transistor and preparation method thereof

Abstract

The invention provides a tunneling field effect transistor and a preparation method thereof. The preparation method at least comprises the following steps that an SOI substrate provided with top layer silicon, an oxygen buried layer and bottom layer silicon is provided, and ion injection is conducted on the two sides of the top layer silicon to form a source electrode and a drain electrode respectively; an intrinsic silicon layer, and a grid medium layer and a grid layer are sequentially formed on the surface of the SOI substrate from bottom to top; a stacking structure is formed by etching the intrinsic silicon layer, the grid medium layer and the grid layer through the photoetching and etching technologies, the stacking structure is partially overlapped with the source electrode and is preset distance away from the drain electrode in the horizontal direction. According to the tunneling field effect transistor and the preparation method of the tunneling field effect transistor, the stacking structure is overlapped with the source electrode so that the tunneling area can be increased, and further a driving current is increased. In addition, the stacking structure is preset distance away from the drain electrode in the horizontal direction, and the bipolar effect in the tunneling field effect transistor can be suppressed through the preset distance, and a subthreshold current is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a tunneling field effect transistor and a preparation method thereof. Background technique [0002] In recent years, microelectronics technology with silicon integrated circuits as the core has developed rapidly. The development of integrated circuit chips basically follows Moore's law, that is, the integration level of semiconductor chips doubles every 18 months. Over the past period of time, the advancement of microelectronics technology has been based on the continuous optimization of the cost-effectiveness of materials, processes and processes. However, scaling down conventional silicon-based CMOS transistors has become increasingly difficult with the development of microelectronics technology. Moreover, most electronic products manufactured using MOSFETs today have the following main problems: First, due to the shortening of the MOSFET channel, the leakage cur...

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Problems solved by technology

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a tunneling field effect transistor and its preparation method, which are used to solve the problem of low driving current and bipolar effect of ordinary tunneling field effect transistors in the prior art. The problem

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