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Novel high-current n-type TFET device with buried layer structure and preparation method thereof

A high-current, layer-structured technology, used in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as poor work function, increased device threshold voltage, etc.

Active Publication Date: 2020-10-30
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in order to ensure that the channel under zero bias can be completely depleted, PNN-TFET requires the channel to be thin enough so that the on-state current of the device is still much smaller than the on-state current of the MOSFET device; in addition, the increase in the work function difference , leading to an increase in the threshold voltage of the device, and the introduction of a serious gate-induced leakage current (GIDL effect) in the off state

Method used

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  • Novel high-current n-type TFET device with buried layer structure and preparation method thereof
  • Novel high-current n-type TFET device with buried layer structure and preparation method thereof
  • Novel high-current n-type TFET device with buried layer structure and preparation method thereof

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Embodiment 1

[0047] figure 1 It is a structural schematic diagram of a novel high-current n-type TFET device with a buried layer structure provided by an embodiment of the present invention, including:

[0048] Substrate 10;

[0049] The surface of the substrate 10 is provided with a source region 20 , a drain region 30 and a channel region 40 ; wherein the source region 20 and the drain region 30 are respectively located at both ends of the channel region 40 ;

[0050]A buried layer 11 is disposed under the channel region 40, the buried layer 11 starts at the junction of the channel region 40 and the source region 20, and the length of the buried layer 11 is shorter than that of the channel the length of zone 40;

[0051] A gate structure 60 is provided above the channel region 40; the gate structure 60 includes a gate electrode 62 and a gate dielectric layer 61 between the gate electrode 62 and the channel region 40;

[0052] A source electrode 21 and a drain electrode 33 are correspo...

Embodiment 2

[0074] On the basis of the first embodiment above, this embodiment provides a method for preparing a novel high-current n-type TFET device with a buried layer structure. Please refer to Figure 4 , Figure 4 It is a schematic diagram of a method for preparing a novel high-current n-type TFET device with a buried layer structure provided by an embodiment of the present invention, including:

[0075] S1: Get p with a certain doping concentration - substrate.

[0076] In this embodiment, the substrate material is lightly doped, and may be a single crystal Ge substrate, Si substrate or other substrate materials.

[0077] S2: In the p - heavily doped p ++ buried layer.

[0078] Specifically, a single crystal Ge substrate can be selected, and photolithography is performed to form a buried layer ion implantation window; ion doping is performed at a position corresponding to the buried layer to form a p-type buried layer; wherein, the buried layer and the substrate are doped with...

Embodiment 3

[0095] The device simulation parameters in the first embodiment are specifically taken below, and the manufacturing method of the present invention will be described in detail.

[0096] See Figure 5a~5h , Figure 5a~5h It is a schematic diagram of the preparation process of a novel high-current n-type TFET device with a buried layer structure provided by an embodiment of the present invention, including:

[0097] Step 1: Select a doping concentration of 1×10 17 cm -3 the p - Type single crystal Ge is the initial material, and it is used as the substrate 101, such as Figure 5a shown.

[0098] Step 2: Perform the first photolithography to form a buried layer ion implantation window in a specific region of the substrate 101; perform selective ion implantation on it, and anneal to activate impurities to form a doping concentration of 1×10 20 cm -3 , a thickness of 10nm P ++ type buried layer 102, such as Figure 5b shown.

[0099] Step 3: On the substrate with the bur...

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Abstract

The invention discloses a novel high-current n-type TFET device with a buried layer structure and a preparation method of the novel high-current n-type TFET device. The n-type TFET device comprises asubstrate, wherein a source region, a drain region and a channel region are arranged on the surface of the substrate, the source region and the drain region are located at the two ends of the channelregion respectively; a buried layer is arranged below the channel region, the buried layer starts from the junction of the channel region and the source region, and the length of the buried layer is smaller than that of the channel region; a gate structure is arranged above the channel region, the gate structure comprises a gate electrode and a gate dielectric layer located between the gate electrode and the channel region; and a source electrode and a drain electrode are correspondingly arranged on the source region and the drain region respectively. According to the n-type TFET device provided by the invention, the requirement on a gate metal work function is reduced, so that the threshold voltage of the device is reduced, and the GIDL effect is inhibited; meanwhile, due to the introduction of a substrate tunneling junction, the tunneling area of the device is increased, the on-state current is improved, and the performance of the device is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a novel high-current n-type TFET device with a buried layer structure and a preparation method thereof. Background technique [0002] With the continuous reduction of CMOS transistor size and the continuous improvement of chip integration density, power consumption has become a key issue limiting the development of integrated circuits. The subthreshold swing represents the speed at which the device transitions from the off state to the on state. The larger the subthreshold swing, the shorter the time the device is in the subthreshold state, and the lower the power consumption of the device. However, limited by the carrier injection mechanism, the minimum limit of the subthreshold swing of MOSFET at room temperature is 60mV / dec, which makes it difficult for traditional micro-nano electronic devices to meet the requirements of modern advanced i...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/10H01L29/78H01L21/336
CPCH01L29/0607H01L29/1033H01L29/78H01L29/66477
Inventor 王斌陈睿罗昭蔺孝堃陈瑶胡辉勇
Owner XIDIAN UNIV
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