232results about How to "Increase the on-state current" patented technology

The embodiment of the invention provides a thin-film transistor, and a preparation method, an array substrate and a display thereof, relating to the field of displaying technology and capable of reducing the current leakage and ensuring the performance reliability of the thin-film transistor while maintaining the high on-state current of the thin-film transistor. The thin-film transistor comprises a grid electrode, a grid insulating layer, an active layer, a source electrode and a drain electrode, wherein the active layer comprises a first active layer and a second active layer, the first active layer is arranged at one side close to the grid insulating layer, the second active layer is arranged at one side close to the source electrode and the drain electrode; the charge carrier mobility of the first active layer is higher than that of the second active layer. The invention provides the production method of the thin-film transistor capable of reducing the current leakage of the thin-film transistor while needing to maintain the high on-state current of the thin-film transistor, and a production method of the array substrate and the display of the thin-film transistor.

The invention provides a thin film transistor, a preparation method for the same and an array substrate, and relates to the technical field of display. The trench length of the thin film transistor can be reduced. The thin film transistor comprises a gate arranged on a substrate, a gate insulating layer, an active layer, a source and a drain, wherein the source and the drain are arranged on the two sides of the active layer along a direction perpendicular to the substrate respectively, and contact with the active layer. The thin film transistor, the preparation method for the same and the array substrate are used for manufacturing a display.

The invention discloses a synaptic transistor based on a two-dimensional semiconductor material and a preparation method of the synaptic transistor. The synaptic transistor comprises an insulating substrate, and a channel, a source electrode, a drain electrode and a gate electrode which are arranged on the substrate, wherein the channel is a two-dimensional semiconductor material; the source electrode and the drain electrode are arranged at the two ends of the channel respectively and form an ohmic contact with the channel material; the gate electrode and an electrical interconnection system formed by the channel, the source electrode and the drain electrode are kept in electronic insulation; an organic electrolyte covers a channel region and most of the gate electrode and comprises an organic carrier capable of being electrically insulated and ions capable of being migrated, and effective ion control of the gate to the channel material is formed. According to the synaptic transistor based on the two-dimensional semiconductor material and the preparation method of the synaptic transistor, an ion attachment-intercalation mechanism is utilized, and the characteristics of large surface area and adjustable resistance value of the two-dimensional material are combined, so that the device shows long-term and short-term synaptic plasticity, and the two characteristics can change witheach other along with the change of a gate signal. Meanwhile, the device has good linearity and ultralow operational power consumption, and the implementation and large-scale integration application of a high-precision neuromorphic device are facilitated.

A semiconductor device is disclosed, and comprises a substrate, a gate stack structure on the substrate, source/drain regions in the substrate at two sides of the gate stack structure, and a channel region between the source/drain regions in the substrate. The source region in the source/drain region comprises a GeSn alloy, and a tunneling dielectric layer optionally exists between the GeSn alloy of the source region and the channel region. By using the semiconductor device and a manufacturing method thereof in the present invention, selective epitaxy is performed, or a precursor is injected and then rapid annealing is performed through laser, to form a GeSn alloy with a narrow band gap, thereby effectively increasing an on-state current of a TFET, and having an important application prospect in a high-performance low-consumption application.

An embodiment of the invention provides a thin film transistor, a manufacturing method thereof, an array substrate and a display device and relates to the technical field of display. On-state current can be increased while leakage current is lowered. The thin film transistor comprises a source electrode, a drain electrode, a grid electrode and a semiconductor active layer, the semiconductor active layer comprises a first sub semiconductor layer and a second sub semiconductor layer, and the first sub semiconductor layer is close to the grid electrode; at least a portion corresponding to an area between the source electrode and the drain electrode in the first sub semiconductor layer is composed of polycrystalline silicon, and a portion corresponding to the area between the source electrode and the drain electrode in the second sub semiconductor layer at least comprises noncrystalline silicon.

The embodiments of the present invention provide a film transistor and the manufacturing method thereof, an array substrate and a display apparatus, relating to the technical field of display and capable of effectively ensuring that while the on-state current is increased, the leakage current is reduced. The film transistor includes a gate electrode provided on a substrate, a source/drain pattern composed of a source electrode and a drain electrode, and an active layer, wherein the active layer comprises a first semiconductor layer and a second semiconductor layer arranged in layers, with the former having a larger electron mobility than the later and the former being closer to the gate electrode than the latter. The semiconductor layer at one side of the active layer and remote from the source/drain pattern has an extended part, compared with the semiconductor layer close to one side of the source/drain pattern, at a position corresponding to the source electrode and/or drain electrode. The source electrode and/or the drain electrode are in contact with the bottom surface of the semiconductor layer in the active layer close to one side of the source/drain pattern and extend to the extended part so that they are in contact with the extended part.

The invention discloses a tunneling field effect transistor based on a two-dimensional material/semiconductor hetero-junction and a preparation method thereof. A device forms an interleaved energy band structure in the off state through the energy band design, namely, a tunneling window is inexistent between the two-dimensional material and the semiconductor material, and the ultra-low off-state current can be acquired; the grid voltage can be applied to regulate an energy band alignment way at the two-dimensional material/semiconductor hetero-junction so that the device can form the staggered energy band structure in the on-state, and the effective tunneling barrier height is a negative value; and meanwhile, the current carrier tunnels to a channel region from a source region to realize the direct tunneling, thereby acquiring large on-state current. The device adopts the highly-doped three-dimensional semiconductor material as the source region material, and the three-dimensional semiconductor material and the metal source electrode are unipotential; since the thickness of the two-dimensional material is ultra-thin, the grid voltage can regulate the two-dimensional material and the energy band at the two-dimensional material/semiconductor hetero-junction interface, thereby acquiring an ideal grid control capacity. The tunneling field effect transistor disclosed by the invention is simple in process, and large in compatibility with the traditional semiconductor process.

The invention discloses a flexible low-voltage organic field effect transistor and a manufacturing method thereof. Three layers of polymers are added between a gate and a semiconductor layer interface to serve as an insulated layer; the overall device comprises a source and drain electrode, a semiconductor, a high-insulation polymer, a high-dielectric constant material polymer, a high-insulation polymer, a gate, and a flexible transparent plastic substrate sequentially from top to bottom; and the dielectric layer with the structure has excellent insulation and good stability. Through measuring electrical properties and a semiconductor particle growth shape, whether the device is a flexible low-voltage organic field effect transistor can be judged. The organic field effect transistor has the advantages of realizing high mobility and large switch ratio under low voltage, maintaining good performance when bias voltage is applied and in a high temperature condition, and having good stability features in different bending modes.

The invention discloses a film transistor array substrate which comprises a plurality of film transistors arranged on one glass substrate in an array manner. Each film transistor comprises a grid electrode formed on the glass substrate, a grid electrode insulating layer covering the grid electrode, an active layer arranged on the grid electrode insulating layer, and a source electrode and a drain electrode which are formed on the active layer, wherein the source electrode and the drain electrode are spaced in a first direction, and the region, corresponding to the interval between the source electrode and the drain electrode, of the active layer is a channel region; the surface, facing the active layer and at least corresponding to the channel region, of the grid electrode insulating layer is provided with a plurality of protruding structures, and a wrinkled surface with a plurality of grooves is formed; and the surface, facing the grid electrode insulating layer, of the active layer is totally engaged with the surface of the grid electrode insulating layer. The invention further discloses a preparation method of the film transistor array substrate and a liquid crystal panel comprising the film transistor array substrate.

The invention relates to a preparation method of a high-mobility transistor based on PMMA doped micro-molecule. The preparation method comprises the following steps: S1, preparing a C8-BTBT and PMMA mixed solution; S2, cleaning a substrate: selecting a P-type heavily-doped silicon slice containing silicon dioxide, cleaning the P-type heavily-doped silicon slice after tailoring the same; S3, preparing a C8-BTBT active layer and a PMMA modification layer: overspreading the C8-BTBT and PMMA mixed solution configured through the step S1 on the substrate by using a dropper, spin-coating for 40s under the rotation speed of 2000-3000rpm; S4, thermally treating the spin-coated film; S5, preparing a molybdenum oxide buffer layer; and S6, preparing the source electrode and the drain electrode. The preparation method disclosed by the invention is simple, the prepared active layer is less in surface defect, the performance of the manufactured transistor device is improved.

The invention discloses a display base plate, a preparation method of the display base plate, and a display device. The display base plate comprises a substrate base plate, a grid line and a data wire, wherein the grid line and the data wire are positioned on the substrate base plate and used for limiting a pixel unit, wherein the pixel unit comprises a thin film transistor and a pixel electrode; the thin film transistor comprises a grid electrode, an active layer and a source/ drain electrode; an assisting layer is also arranged on the substrate base plate; a first groove is arranged in the assisting layer; the grid electrode and the grid line are both positioned into the first groove. With the adoption of the display base plate, that the coverage characteristic of a grid insulating layer at the sidewall is lowered down as the thickness of the grid electrode layer increases and even the risk of wrinkling or breaking occurs can be reduced; moreover, a thin grid insulating layer can be adopted although a thick grid electrode layer is put into use because of the protection of the assisting layer, and therefore, the ON-state current of the thin film transistor can be improved.

The invention provides a tunneling transistor structure. The tunneling transistor structure comprises a substrate, a silicon strip, a drain electrode area, a source electrode area, a gate dielectric layer and a grid electrode, wherein the silicone strip is formed on the substrate; the drain electrode area is formed at one side of the silicon strip; the source electrode area is equipped with a first groove in which the silicon strip is contained; the grate dielectric layer is formed on the source electrode area and partially covers the source electrode area; the grid electrode is equipped with a second groove in which the gate dielectric layer is contained; the cross section of the second groove is the same as that of the first groove; when in tunneling, the first groove tunnels under the effect of the second groove to form a tunneling current. The invention also provides a manufacturing method of the tunneling transistor structure. According to the tunneling transistor structure, the structures of the source electrode area and the grid electrode are changed; when in tunneling, the tunneling area of the source electrode area is expanded under the effect of the grid electrode, and point tunneling and line tunneling occur in the first groove; therefore, both the tunneling area and the tunneling portability are raised through the structure, and as a result, the on-state current of the whole device can be improved.

The invention belongs to the field of semiconductor memory manufacturing and particularly relates to a three-dimensional semiconductor memory based on vertical channels of two-dimensional semiconductor materials and a preparation method thereof. The three-dimensional semiconductor memory comprises a plurality of three-dimensional storage strings in a vertical direction, and each three-dimensionalmemory string includes a semiconductor vertical channel whose length is determined by the number of layers of memory three-dimensional stack. The vertical channel materials comprise one or more two-dimensional semiconductor materials and protection layers on the surfaces of the two-dimensional semiconductor materials. The protection layers are used for supporting and protecting the two-dimensionalsemiconductor materials, and the carrier mobility of the two-dimensional semiconductor materials is higher than that of amorphous silicon. According to the invention, the two-dimensional materials are used as memory channels, higher memory cell on-state current can be provided, and therefore, the operational power consumption of the memory is reduced.

The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device. The array substrate comprises a first gate metal layer, a first gate insulating layer on the first gate metal layer, an active layer which is arranged on the first gate insulating layer and corresponds to the first gate metal layer, an etching barrier layer on the active layer, a source and drain metal layer comprising a source and a drain, a second gate insulating layer on the source and drain metal layer and a second gate metal layer on the second gate insulating layer, wherein the source and the drain are in contact with the two sides of the active layer respectively and are separated on the etching barrier layer. By means of the array substrate, the manufacturing method of the array substrate and the display device, the TFT characteristic can be optimized, the gate line resistance can be reduced, light irradiating the active layer can be shielded, IR Drop and TFT threshold voltage excursion and generation of the light leakage current of the active layer can be easily restrained, and the performance of the display device can be promoted.

The invention discloses a knot-free nanowire field effect transistor which comprises a channel, a source region and a drain region. The source region is arranged at one end of the channel, and the drain region is arranged at the other end of the channel; the outer surface of the channel is covered by a gate oxide layer which is covered by a grid electrode layer; and the grid electrode layer comprises a first grid electrode layer which is close to the source region and a second grid electrode layer which is close to the drain region. Compared with the prior art, the embodiment of the invention has the advantages that: by adopting a split gate structure, the speed of the charge carrier in the channel of the knot-free nanowire field effect transistor is increased, so the on-state current is increased, the off-state current of a device is reduced irrespective of the influence of the threshold voltage, the influence of the drain region on the device is screened, the drain induced barrier lowering effect is obviously weakened and the driving ability of the current is improved. Meanwhile, with the split gate, the transconductance feature of the knot-free nanowire field effect transistor under low voltage is obviously improved.

The invention discloses a ferro-electric field effect transistor based on a structured carbon nano tube striped array and a manufacturing method of the ferro-electric field effect transistor. According to the unit structure of the transistor, a bottom electrode layer (1) is arranged on the bottom layer, a ferro-electric film insulated gate layer (2) and a structured carbon nano tube striped array channel layer (3) are sequentially arranged on the middle layer, and a top layer is arranged on the structured carbon nano tube striped array channel layer (3) and comprises a transistor source electrode (4) and a transistor drain electrode (5); carbon nano tubes are single-walled carbon nano tubes, or double-walled carbon nano tubes or multi-walled carbon nano tubes. According to the ferro-electric field effect transistor, the on-state current and the switch ratio are large, carrier mobility is high, the starting voltage is small, the storage window is wide, and meanwhile the ferro-electric field effect transistor has the advantages of being simple in structure and a buffering layer is not needed, interface contact between a ferro-electric layer and a semiconductor layer is good, and large-area soft devices are easy to obtain. The manufacturing method is simple in technology, convenient to operate and low in cost and dispense with expensive equipment, and large-area and large-scale industrial production is easy to realize.

The invention discloses an embedding layer heterojunction tunneling field effect transistor and a manufacturing method of the embedding layer heterojunction tunneling field effect transistor, and belongs to the field of field effect transistor logic devices in the CMOS ultra large scale integration (ULSI). The two sides of a vertical channel region of the embedding layer heterojunction tunneling field effect transistor are provided with control gates respectively. The control gates are of an L-shaped structure. Gate medium layers are arranged between the two control gates and the vertical channel region. A tunneling source region is arranged above the vertical channel region. An embedding layer is arranged between the tunneling source region and the channel region. The thickness of the embedding layer is smaller than the width of a space charge region at a tunneling junction. A split-level heterojunction is formed on the interface position of the tunneling source region and the embedding layer. A staggered heterojunction is formed on the interface position of the embedding layer and the channel region. Compared with an existing TFET, by means of the embedding layer heterojunction tunneling field effect transistor, the device on-state current is increased remarkably, and the lower off-state current is kept.

The invention discloses a thin film transistor, a manufacture method thereof, an array substrate and a display device, which belongs to the technical field of display. The thin film transistor comprises a substrate. A gate is formed on the substrate. A gate insulating layer is formed on the substrate with the gate. An active layer and a source drain metal pattern are formed on the substrate with the gate insulating layer. The active layer comprises a polysilicon pattern and an amorphous silicon pattern on the polysilicon pattern. The source drain metal pattern comprises a source and a drain. The source contacts the polysilicon pattern and the amorphous silicon pattern. The drain contacts the polysilicon pattern and the amorphous silicon pattern. According to the invention, the problems of small open current and low charging rate of the thin film transistor are solved; the open current of the thin film transistor is increased; and the charging rate is improved. The thin film transistor, the manufacture method thereof, the array substrate and the display device are applied to the array substrate.

The invention provides a junctionless tunneling field effect transistor and a formation method thereof. The junctionless tunneling field effect transistor includes the following components of: a substrate; a liner layer arranged on the substrate; a channel layer which is arranged on the liner layer and includes a channel region arranged in the middle as well as a source region and a drain region arranged at two sides of the channel region, wherein the channel region, the source region and the drain region have the same doping type; a source which coats on the upper surface, a side surface and the lower surface of the source region and coats the lower surface of the channel region, and is in Schottky contact with the channel region; a drain which coats the upper surface and a side surface of the drain region; and a gate stack structure which is located on the channel region. The junctionless tunneling field effect transistor has the advantages of simple structure, large tunneling current, capability of effectively suppressing a short channel effect and the like. The invention also provides a formation method of the junctionless tunneling field effect transistor.

The invention provides a tunneling field effect transistor with an electric field concentration effect to enhance the on state current and belongs to the field of semiconductor apparatuses. The tunneling field effect transistor provided by the invention comprises a semiconductor substrate 1, a source region 2, an intrinsic region 3, a drain region 4, a grid oxide layer 5, a metal grid 6 and a side wall 9 and further comprises a medium block 10 which is arranged in the intrinsic region, wherein the medium block 10 is arranged on an interface of the intrinsic region and the source region, and the medium block can be used for changing electric field distribution in a tunnel junction position, so that the electric field line at the tunnel junction is concentrated so as to enhance the on state current.

The invention discloses a thin film transistor and a manufacturing method thereof and a display device, and belongs to the field of a semiconductor. The thin film transistor comprises a first active layer, a source electrode, a drain electrode, a grid electrode and a second active layer, wherein the source electrode, the drain electrode and the grid electrode are arranged on the first active layer at intervals; the grid electrode is arranged between the source electrode and the drain electrode; the second active layer is arranged on the grid electrode, the source electrode and the drain electrode; the source electrode and the drain electrode are connected with the first active layer and the second active layer; the grid electrode is insulated from the first active layer, the second active layer, the source electrode and the drain electrode; when a voltage is applied to the grid electrode, the source electrode and the drain electrode can be conducted through the first active layer, and the source electrode and the drain electrode can also be conducted through the second active layer; and when the source electrode and the drain electrode are conducted in the thin film transistor, the source electrode and the drain electrode can be conducted through the first active layer and the second active layer simultaneously, so that higher current can flow between the source electrode and the drain electrode, and on-state current of the thin film transistor can be improved.