Embedding layer heterojunction tunneling field effect transistor and manufacturing method thereof

Abstract

The invention discloses an embedding layer heterojunction tunneling field effect transistor and a manufacturing method of the embedding layer heterojunction tunneling field effect transistor, and belongs to the field of field effect transistor logic devices in the CMOS ultra large scale integration (ULSI). The two sides of a vertical channel region of the embedding layer heterojunction tunneling field effect transistor are provided with control gates respectively. The control gates are of an L-shaped structure. Gate medium layers are arranged between the two control gates and the vertical channel region. A tunneling source region is arranged above the vertical channel region. An embedding layer is arranged between the tunneling source region and the channel region. The thickness of the embedding layer is smaller than the width of a space charge region at a tunneling junction. A split-level heterojunction is formed on the interface position of the tunneling source region and the embedding layer. A staggered heterojunction is formed on the interface position of the embedding layer and the channel region. Compared with an existing TFET, by means of the embedding layer heterojunction tunneling field effect transistor, the device on-state current is increased remarkably, and the lower off-state current is kept.

Description

technical field [0001] The invention belongs to the field of CMOS ultra large scale integrated circuit (ULSI) field effect transistor logic devices, and in particular relates to an embedded layer heterojunction tunneling field effect transistor and a preparation method thereof. Background technique [0002] Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, existing MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT / q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the entire chip continue...

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Problems solved by technology

However, since the staggered-layer heterojunction always has a band-band tunneling window in the off-state of the device, it will lead to a large off-state current, which will reduce the current switching ratio of the device.

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