204results about How to "High switching ratio" patented technology

The invention discloses a method for preparing a metal chalcogenide film. The method is used for growing the metal chalcogenide film on a substrate with the vapor deposition process by using a chalcogen source and a metal element source and comprises the following steps of: providing three temperature zones, wherein the temperature of the three temperature zones can be controlled independently, and the chalcogen source, the metal element source and the substrate are put in the three temperature zones respectively; controlling the three temperature zones, evaporating the chalcogen source to generate the chalcogen source steam, evaporating the metal element source to generate the metal element source steam, and heating the substrate to the predetermined deposition temperature; providing a carrier gas, and enabling the carrier gas to flow through the three temperature zones in sequence to deliver the metal element source steam to the substrate to deposit and grow so as to form the metal chalcogenide film. The method disclosed by the invention is simple, dispenses with the original complex step of introducing a nucleation site and effectively ensures the purity and the surface cleanness of a sample. The metal chalcogenide film prepared by adopting the method has high quality.

The invention relates to a high-dielectric-constant gate dielectric composite channel field effect transistor device and belongs to the technical field of micro-electronics new materials and devices. The device comprises a substrate, a high-dielectric-constant gate dielectric, a graphical graphene conducting channel and a graphical molybdenum sulfide (MoS2) conducting channel which are sequentially stacked, and comprises a metal source electrode and a metal drain electrode which are arranged on the composite conducting channel. According to a preparing method, the mode of the atomic layer deposition technology (ALD) is directly utilized, and a high-dielectric-constant (high-k) material grows on the Si substrate. As the graphene/ molybdenum sulfide (MoS2) composite channels are adopted, the larger migration rate and the larger switch ratio can be obtained, and the electric property of the device is improved.

The invention discloses an aggregation-induced emission type diarylethene fluorescent molecular switch and a preparation method and application thereof. The aggregation-induced emission type diarylethene fluorescent molecular switch is characterized in that an AIE radical is introduced to gain solid or aggregation strong emission capacity; two diarylethene can be used for quickly quenching fluorescence of fluorescent radicals which aggregate in the surrounding under the irradiation of ultraviolet rays or visible light, thus achieving the purpose of high fluorescent switch ratio. According to the light control type AIE-effect fluorescent molecular switch, the limitation that traditional fluorescent chromophore leads to fluorescence quenching is broken; in addition, the fluorescent molecularswitch in solid and aggregation state has the advantages of being high in switch ratio and high in fluorescence quenching efficiency by being compared with the fluorescent molecular switch in solution state; the fluorescent molecular switch is applicable to information storage under solid state and photoelectric devices and has potential application in biosensing and fluorescence imaging.

The invention discloses a graphene/silicon/graphene-based avalanche photodetector and a manufacturing method thereof. The avalanche photodetector comprises an n-type silicon substrate, a silicon dioxide isolation layer, a silicon dioxide window, a silicon dioxide insulation layer, a top electrode, a graphene interdigital electrode film and an anti-reflection layer. Graphene serves the transparent interdigital electrode and together with the silicon substrate, the photodetector of an MSM-type structure is formed. The photodetector can carry out wide spectrum detection, the problem that the traditional silicon-based PIN junction is low to ultraviolet light detection response can be solved; the anti-reflection layer enhances absorption of incident lights, and photocurrent is enhanced; under the effect of large reverse bias, a strong electric field is generated among the grapheme interdigital electrodes, collision ionization is likely to happen to photocarrier and silicon lattice, and high gain is obtained. The graphene/silicon/graphene-based avalanche photodetector and a manufacturing method thereof have the advantages of high response degree, quick response speed, large internal gain, small switch ratio and low power consumption.

The invention belongs to the technical field of thin film transistors, and relates to a method for preparing a thin film transistor. The method comprises the following steps: by adopting indium-zinc alloy or indium-zinc oxide as a target material, under the room temperature, growing an indium-zinc oxide semiconductor thin film with a transparent amorphous structure on a substrate through magnetron sputtering technology, and forming a channel layer of the thin film transistor; preparing a source electrode and a drain electrode by adopting a thermal evaporation method; covering a layer of organic medium layer thin film manufactured by polyvinylpyrrolidone organic solution on the source electrode and the drain electrode by adopting a hauling or spinning method; and preparing a gate electrode on the organic medium layer thin film by adopting the thermal evaporation method. The atomic ratio of In to Zn in the target material is 0.5 to 5.0. The method can prepare a novel transparent thin film transistor with good electronic optical performance, has low preparation temperature and simple process, is favorable for large-area production, and has wide application prospect.

The invention provides overlong carbon nanotubes and a preparation method thereof. The method provided by the invention comprises the following steps of: 1) coating ethanol solution or aqueous solution of a metal chloride of at least one of Fe, Mo, Cu and Cr on a substrate, placing the substrate in a reactor and heating the reactor to 600 to 1,000 DEG C, introducing a hydrogen gas or mixed gas ofthe hydrogen gas and an inert gas into the reactor to perform reduction reaction; and 2) heating the reactor to 800 to 1,100 DEG C after the reduction reaction is finished, and introducing mixed gas of a carbon source gas, the hydrogen gas and vapor into the reactor and reacting to obtain the carbon nanotubes. The overlong carbon nanotubes prepared by the method have perfect structures and superior electric and mechanical properties.

The invention discloses an aluminum zinc oxide amorphous semiconductor film material and a preparation method and application thereof and belongs to the technical field of semiconductor integrated circuits and manufacture thereof. The amorphous semiconductor film comprises, by mole percent content, 85-98% of zinc element, 1-10% of aluminum element and 1-14% of rare earth element, wherein the rare earth element is at least one of Gd, Lu, Y and Sc. A radio frequency magnetron sputtering method is adopted to prepare the aluminum zinc oxide film material doped with the rare earth element, the voltage division ratio of oxygen atmosphere is adjusted in the sputtering process to form a channel material which has amorphous characteristics and is high in migration rate. The preparation method is compatible with a traditional complementary metal oxide semiconductor (CMOS) process, and a rare earth doped oxide semiconductor film transistor can be prepared, is high in practical value and can be applied to future thin film transistor (TFT) integrated circuits.

A stepped gate-dielectric double-layer graphene field effect transistor comprises a bottom gate electrode, a bottom gate dielectric layer, a double-layer graphene active region, a metal source electrode, a metal drain electrode, a stepped top gate dielectric layer and a top gate electrode. The bottom gate dielectric layer is located on the bottom gate electrode, the double-layer graphene active region is located on the bottom gate dielectric layer, the metal source electrode and the metal drain electrode are located at two ends of the double-layer graphene active region respectively and cover the bottom gate dielectric layer and part of the double-layer graphene active region at the same time, the stepped top gate dielectric layer covers the metal source electrode, the metal drain electrode and graphene between the two electrodes, the top gate electrode only covers the top of the stepped top gate dielectric layer partially, and the distance between the top gate electrode and the edge of the metal source electrode is equal to that between the top gate electrode and the edge of the metal drain electrode. By introduction of the stepped top gate dielectric layer, a tunneling window between a source region and a gate-controlled trench under an off state is reduced effectively, so that small off-state current is obtained, and on-off ratio of a device is increased.

The invention discloses a flexible low-voltage organic field effect transistor and a manufacturing method thereof. Three layers of polymers are added between a gate and a semiconductor layer interface to serve as an insulated layer; the overall device comprises a source and drain electrode, a semiconductor, a high-insulation polymer, a high-dielectric constant material polymer, a high-insulation polymer, a gate, and a flexible transparent plastic substrate sequentially from top to bottom; and the dielectric layer with the structure has excellent insulation and good stability. Through measuring electrical properties and a semiconductor particle growth shape, whether the device is a flexible low-voltage organic field effect transistor can be judged. The organic field effect transistor has the advantages of realizing high mobility and large switch ratio under low voltage, maintaining good performance when bias voltage is applied and in a high temperature condition, and having good stability features in different bending modes.

The invention relates to a thermal switch for conduction-cooled superconducting magnet, characterized in that it is the cylinder closed accommodator, comprising upper round plate [8], low round plate [10] and cylinder with thin wall [9]; the cylinder with thin wall [9] is the wall surface of cylinder closed accommodator; parallel red copper fins arranged in certain distance are set on inner surfaces of upper round plate [8] and lower round plate [10], fins on upper and lower round plates insert in cross and there is gap between adjacent fins; upper round plate [8] and lower round plate [10] are made of high thermal conductivity material and the cylinder with thin wall [9] is made of low thermal conductivity material; upper round plate [8], lower round plate [10] and cylinder with thin wall [9] are connected by positive and negative screw thread and the length of thermal switch [4] on the axial direction is controlled by the rotating depth of cylinder with thin wall [9]. The invention is provided with no need to vacuum pumping, strong conduction ability, big on-off ratio and no need to be controlled by outside. It can shorten the cooling time of prior conducting cooled magnet system.

Disclosed is a method for depositing ultrathin layers of an organic semiconductor material on a support, and its applications in fabrication of electronic devices like OEFT and diodes. In the method, a source of an organic semiconductor material and a support are spaced from each other in a vacuum chamber and subjected to a temperature gradient, and the epitaxy initiates due to a van der Waals interaction between the organic molecules and the support. The ultrathin crystalline layers of the organic semiconductor material can be only a-few-molecule thick and even one-molecule thick in total. Further disclosed is a layered structure produced by said method and use of the layered structure in fabrication of logic gates.

The invention discloses a ferro-electric field effect transistor based on a structured carbon nano tube striped array and a manufacturing method of the ferro-electric field effect transistor. According to the unit structure of the transistor, a bottom electrode layer (1) is arranged on the bottom layer, a ferro-electric film insulated gate layer (2) and a structured carbon nano tube striped array channel layer (3) are sequentially arranged on the middle layer, and a top layer is arranged on the structured carbon nano tube striped array channel layer (3) and comprises a transistor source electrode (4) and a transistor drain electrode (5); carbon nano tubes are single-walled carbon nano tubes, or double-walled carbon nano tubes or multi-walled carbon nano tubes. According to the ferro-electric field effect transistor, the on-state current and the switch ratio are large, carrier mobility is high, the starting voltage is small, the storage window is wide, and meanwhile the ferro-electric field effect transistor has the advantages of being simple in structure and a buffering layer is not needed, interface contact between a ferro-electric layer and a semiconductor layer is good, and large-area soft devices are easy to obtain. The manufacturing method is simple in technology, convenient to operate and low in cost and dispense with expensive equipment, and large-area and large-scale industrial production is easy to realize.

The embodiment of the invention provides a memory device, a manufacturing method of the memory device and an electronic device. The memory device comprises a resistive material, a first conductive layer sequentially stacked, a magnetic tunnel junction and a second conductive layer, wherein the first conductive layer, the magnetic tunnel junction and the second conductive layer are sequentially stacked; the resistive material is positioned between the first conductive layer and the second conductive layer; the resistive material is adhered to the edge of the magnetic tunnel junction to wrap themagnetic tunnel junction; the magnetic tunnel junction comprises a magnetic fixing layer, a barrier layer and a magnetic free layer which are sequentially stacked; a conductive channel is formed in the region near the magnetic tunnel junction in the resistive material and two ends of the conductive channel are respectively connected to the magnetic fixing layer and the magnetic free layer. The memory device provided by the embodiment of the invention can equivalently be the parallel connection of the magnetic memory unit and the impedance memory unit in the electrical structure, and has the advantages of high read-write speed, unlimited read-write operation, high switching ratio and the like.

The invention discloses a preparation method of a schottky gate field effect transistor. According to the preparation method, a two-dimensional material is prepared on a substrate firstly, then the substrate and the two-dimensional material are coated with photoresist in a spin coating manner, and photoetching exposure and developing are performed to expose source and drain electrode windows; metal is coated, and the photoresist is washed off, and next, annealing in gas atmosphere is performed to form a source electrode and a drain electrode; next, the whole piece of a sample is coated with photoresist in a spin coating manner, and photoetching exposure and developing are performed to expose a gate electrode window; and next, metal is coated, and the photoresist is washed off to form the schottky gate field effect transistor. The schottky gate field effect transistor has the advantages of small dimensions, high switch ratio, high mobility, capability of well eliminating a short-channel effect and the like, so that the application field of a two-dimensional material device can be expanded.

The invention relates to a preparation method of an enhanced field effect transistor based on a two-dimensional planar heterojunction, and relates to the application field of microelectronic devices.The preparation method comprises the steps of transferring a graphene film to a monocrystalline silicon wafer substrate with an oxide layer by adopting wet transfer; uniformly spinning a photoresist on the graphene film, and transferring a pattern to the photoresist through exposure; etching the graphene film into graphene strips, and removing the photoresist; enabling the substrate with the graphene strips to serve as a substrate for growth, growing an MX2 type single-layer or few-layer material according to a CVD method, and forming a graphene-MX2-graphene in-plane heterojunction; and evaporating and depositing Ti/Au metal on the graphene-MX2-graphene in-plane heterojunction to obtain a two-dimensional planar heterojunction enhanced field effect transistor. The field effect transistor with a high switching ratio is obtained by combining the semi-metal material graphene with high carrier mobility and the MX2 two-dimensional material with the band gap being adjustable along with variations in number of layers, and the field effect transistor has excellent characteristics of very small dark current when being applied to photoelectric detection.

The invention relates to a method for preparing a high-temperature coefficient and high-stability room temperature switch nanocomposite and the performance of the high-temperature coefficient and high-stability room temperature switch nanocomposite. The high-temperature coefficient and high-stability room temperature switch nanocomposite is a novel intelligent nano composite functional material. According to the method, a nano material with high heat, electric and magnetic transmission characteristics and an insulating base solution with a fixed crystallization point are combined flexibly to prepare the switch nanocomposite; and the interface affinity of the switch nanocomposite and the base solution is enhanced by the surface modification of the nano material, so that the switch ratio and stability of the nanocomposite are improved greatly. The intelligent nano composite functional material with high practicality has a broad application prospect in fields of energy, biological medical treatment and the like.

Provided is an indium tin zinc oxide homogeneous thin film transistor and a preparation method of the thin film transistor. The thin film transistor comprises a substrate, a grid electrode, an insulating layer, a channel layer, a source electrode and a drain electrode. The thin film transistor is characterized in that material of the channel layer, the source electrode and the drain electrode is indium tin zinc oxide. The indium tin zinc oxide is indium tin zinc oxide ceramic target material made of In2O3, SnO2 and ZnO powders via ball grinding and uniform mixing, and technologies of molding, sintering, etc. The atomic number ratio of indium, tin and zinc in the indium tin zinc oxide ceramic target material is a: b: c=35-88: 8-35: 2-25. The indium tin zinc oxide ceramic target material is deposited into a thin film by utilizing a magnetron sputtering mode. The thin film transistor is simple in preparation technology and suitable for industrial production. The surface of an amorphous electrode is great in flatness so as to be better in contact with the interface of the channel layer. Therefore, injection of carriers is easier, mobility is high and on-off ratio is high.

The invention discloses large-area molecular crystal and a preparation method thereof. The preparation method for the large-area molecular crystal comprises the following steps that an organic semiconductor solution is placed on a substrate with a hydrophobic property, a substrate with a hydrophily property covers the substrate with the hydrophobic property, and after growth, molecular crystal canbe obtained on the substrate with the hydrophily property; the organic semiconductor solution adopts at least one of chlorobenzene solvent, trichloromethane solvent, dichlorobenzene solvent and xylene solvent; the mass volume density of the organic semiconductor solution is 0.01 mg/mL-15 mg/mL; the solutes of the organic semiconductor solution are organic semiconductor molecules. The large-area molecular crystal has the advantages of a large area, high uniformity and a flat surface, a field effect transistor prepared by the large-area two-dimensional molecular crystal has higher carrier mobility rate and lower threshold voltage, and solid foundation is laid for the preparation of later P-N heterojunction.