28results about How to "High switching ratio" patented technology

The invention provides a freeze-thaw enhanced low-energy PEDOT: PSS composite fiber-based artificial synapse transistor and application thereof.The fiber-based artificial synapse transistor is composed of a source-drain fiber electrode, a grid fiber electrode and an ionic gel electrolyte, the source-drain fiber electrode and the grid fiber electrode are prepared from PEDOT: PSS composite fibers, PEDOT: PSS, an anti-freezing agent and a polymer serve as base materials, and the ionic gel electrolyte is prepared from PEDOT: PSS composite fibers. The anisotropic composite fiber electrode which is high in strength, short in energy dissipation path and stretchable is prepared through freeze-thaw pretreatment and a wet spinning technology. The freeze-thaw enhanced low-energy consumption PEDOT: PSS composite fiber-based artificial synapse transistor provided by the invention is high in switching ratio, high in response rate, low in energy consumption, excellent in synapse plasticity and good in pulse cycle stability, and has a huge application prospect in the fields of brain-computer interfaces, human-computer interaction, smart medical treatment, intelligent electronic fabrics and the like.

The invention provides a thermoelectric driving fiber-based organic electrochemical synapse transistor and a preparation method and application thereof, and the thermoelectric driving fiber-based organic electrochemical synapse transistor is composed of a thermoelectric energy supply device, a fiber-based organic electrochemical synapse transistor and wires for connecting all parts. The thermoelectric energy supply device comprises a P-type thermoelectric fiber and an N-type thermoelectric material, and the fiber-based organic electrochemical synaptic transistor comprises a source-drain fiber electrode, a grid fiber electrode and an ionic gel electrolyte. According to the thermoelectric energy supply device prepared based on the Seebeck effect, conversion from heat energy of the human body to electric energy can be achieved, and stable energy supply to the synaptic transistor can be achieved. The integration of the thermoelectric energy supply device and the fiber-based organic electrochemical synaptic transistor has a wide application prospect in the fields of medical treatment, intelligent materials and wearable equipment.

The invention relates to the technical field of photoelectric devices, in particular to a negative capacitance tunneling phototransistor and a preparation method and application thereof. The negative capacitance tunneling phototransistor is of a structure combining a ferroelectric material and a low-dimensional semiconductor heterojunction material, the characteristics of the ferroelectric material are combined with the tunneling effect and the photoelectric characteristic of a low-dimensional semiconductor heterojunction, and a hafnium oxide-based ferroelectric gate dielectric is used for replacing a gate dielectric layer of a traditional phototransistor. A negative capacitance effect is provided in the grid structure of the negative capacitance tunneling phototransistor so as to improve the performance of the device; through the negative capacitance effect of the ferroelectric material, the electrical performance of the tunneling field effect transistor is enhanced, the switching ratio and the on-state current of the device are improved, the sub-threshold swing of the device is further reduced, and the photoelectric responsivity and the response speed of the device are improved at the same time. Due to the arrangement of the grid electrode and the low-dimensional semiconductor heterojunction, the purposes of ultralow subthreshold swing and no hysteresis are achieved. In addition, the device has the characteristics of good stability, simple structure, easy preparation and the like.

The invention belongs to the technical field of thermal switches, and particularly relates to an expansion type thermal switch based on a paper-cut structure, which comprises a thermal expansion paper-cut structure, the thermal expansion paper-cut structure is a central symmetry structure, two ends of the thermal expansion paper-cut structure are fixedly connected through a fixing plate, and the top end of the thermal expansion paper-cut structure is fixedly connected with the bottom end of a fixed heat source; the negative thermal expansion paper-cut structure is of a central symmetry structure, the two ends of the negative thermal expansion paper-cut structure are fixedly connected through a fixing plate, and the bottom end of the negative thermal expansion paper-cut structure is fixedly connected with the top end of the fixed cold source; the thermal expansion paper-cut structure and the negative thermal expansion paper-cut structure are horizontally arranged in parallel, a first gap is reserved between the bottom end of the thermal expansion paper-cut structure and the top end of the fixed cold source, and a second gap is reserved between the top end of the negative thermal expansion paper-cut structure and the bottom end of the fixed heat source. The invention has the advantages of larger thermal stroke, extremely small contact thermal resistance, larger switch ratio and long service life in overheat and overcold space environments.

The invention discloses a volatile threshold switching device based on an atomic-scale geometric confinement layer and a preparation method thereof. The device comprises a substrate layer, a bottom electrode layer, a functional active layer, a geometric confinement layer and a top electrode layer which are stacked in sequence, the functional active layer is used for providing active metal ions to form conductive filaments; the functional active layer is made of a two-dimensional layered ferroelectric material; the geometric confinement layer is made of hexagonal boron nitride sheets, and the thickness range of the hexagonal boron nitride sheets is 1-5 hexagonal boron nitride atomic layers. According to the invention, the h-BN material with atomic-scale lattice defects is introduced as the geometric confinement layer, and the diameter of the conductive filament formed by copper ions in the functional active layer is physically limited by using the atomic-scale ion sieve effect of the h-BN material, so that the problem of failure caused by overgrowth of the filament in a traditional device is solved.

The invention relates to the technical field of integrated circuit manufacturing, and discloses a low-dielectric film based on a layered compound and a preparation method and application thereof. The invention provides a layered compound: [Mx (OH) y] z + [(An-) z / n]. MH2O or [M1x1M2x2 (OH) y] z + [(An-) z / n]. MH2O, where [Mx (OH) y] z + or [M1x1M2x2 (OH) y] z + constitutes a positively charged laminate, an anion An-can be inserted by the expanded interlayer spacing; the invention further discloses a preparation method of the low-dielectric film based on the layered compound. The film has excellent dielectric properties (klt; 1.9), a low dielectric loss (lt; 0.02), the insulation property is good, and meanwhile, the excellent Young's modulus (YMgt; 20 GPa), the mechanical strength meets the requirements of a rear-end interconnection medium, and the material has a wide practical application prospect in the chip rear-end interconnection industry; meanwhile, the material can be used as a transistor insulating layer material, interface traps of a thin film transistor insulating layer and an active layer are reduced, and the carrier mobility and on-off ratio of a transistor are improved.

This invention discloses a high-mobility spin field-effect transistor (SFET), comprising a source electrode, a drain electrode, a gate electrode, a semiconductor channel, and a substrate. Compared to existing SFETs based on a single semiconductor channel, this semiconductor channel structure offers advantages such as tunable band structure, high mobility, tunable carrier concentration and type, and long spin diffusion length. Compared to traditional substrate-based SFETs, this invention introduces a substrate with piezoelectric properties, allowing for the modulation of carrier spin transport within the semiconductor channel through the surface polarization electric field of the substrate. This effectively reduces the turn-on or turn-off voltage and improves gate control. Compared to existing SFET fabrication processes, this invention optimizes the crystal quality of the spin tunneling layer, increases carrier spin polarization, thereby improving the device's on / off ratio and reducing operating current.

The invention belongs to the field of memristors, and discloses a memristor with a high on-off ratio and low off-state current density and a preparation method thereof.The preparation method comprises the following steps that an ITO substrate with the hydroxylated surface is soaked in an ethanol solution of 3-aminopropyltriethoxysilane; 3-aminopropyltriethoxysilane molecules are modified on the surface of the ITO substrate, and the ITO substrate with positive electricity on the surface is obtained; the method comprises the following steps: soaking an ITO substrate with a positively charged surface in a gold nanoparticle colloidal solution to obtain a substrate assembled with gold nanoparticles, spin-coating polymethyl methacrylate on the surface of the substrate assembled with the gold nanoparticles, baking until the substrate is dry, and then plating an aluminum film to obtain the memristor with high on-off ratio and low off-state current density. The memristor disclosed by the invention has an ultrahigh switch ratio and ultralow off-state current density at the same time, can be stably converted between a high-resistance state and a low-resistance state, and has a long-time retention characteristic and good process repeatability.

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the substrate comprises a plurality of active columns arranged in an array, each active column comprises a channel region, and the side wall of each channel region is provided with a grid accommodating groove; a plurality of gates; the grid electrode wraps the channel region corresponding to the active column, and the grid electrode at least fills the grid electrode accommodating groove. The semiconductor structure has relatively good grid control capability and relatively high switch ratio, and is beneficial to improving the electrical performance of a semiconductor device.

This invention discloses a single-pixel reconfigurable dual-mode phototransistor and its fabrication method, along with a pixel array and image edge extraction method. Different polarities are applied to the single-pixel reconfigurable dual-mode phototransistor. Based on a floating base region photogenerated charge accumulation—barrier modulation—transistor gain—Schottky junction photosensitive coupling mechanism, the same pixel switches between two operating modes. Mode one is a switching mode with low dark current and a high on / off ratio threshold triggering function; mode two is a linear mode with a linear analog response and current gain. Utilizing this dual-mode operating mechanism, a sparse operator image edge extraction method of "first screening, then precise measurement" is implemented, reducing system computation and readout overhead at the device level.

The present invention provides an amorphous carbon-coated transition metal sulfide nanosheet and a preparation method thereof, the method mainly comprising the following steps: adding a two-dimensional layered transition metal sulfide to a resin and mixing by stirring in a water bath; peeling by a three-roll differential grinder, collecting from a discharge roller after repeated peeling cycles; removing part of the resin by alcohol dissolution, adding alcohol, and centrifuging and removing impurities by stirring and ultrasonic assistance in a centrifuge tube; placing the substance obtained after alcohol washing in a freeze dryer to obtain a flaky structure; and heat treating under an argon atmosphere to obtain an amorphous carbon-coated transition metal sulfide nanosheet. Compared with the prior art, the material prepared by the present invention has the characteristics of adjustable structure, good conductivity, excellent performance, good stability, etc., which can meet the application requirements of new materials in the fields of battery energy storage, electronic devices and catalysis.

An embodiment of the present application proposes a phase change memory and a manufacturing method thereof, wherein the phase change memory comprises: a phase change memory unit, wherein the phase change memory unit comprises at least a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately; the material of the first sub-gating layer comprises at least germanium, a chalcogen element, and a first doping element; wherein the chalcogen element comprises sulfur and / or selenium; the material of the second sub-gating layer comprises a preset metal element; when the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

The invention relates to the technical field of inorganic semiconductor nanomaterials, in particular to a flexible transistor based on a comprehensive two-dimensional material and a preparation method and application thereof, and the flexible transistor comprises a first graphene nanosheet, a hexagonal boron nitride nanosheet, a molybdenum disulfide nanosheet, a second graphene nanosheet and a third graphene nanosheet, the first graphene nanosheet, the hexagonal boron nitride nanosheet and the molybdenum disulfide nanosheet are sequentially arranged from bottom to top in the thickness direction of the transistor, and the second graphene nanosheet and the third graphene nanosheet are arranged on the molybdenum disulfide nanosheet at intervals. A transverse conducting channel is formed between the second graphene nanosheet and the third graphene nanosheet; the first graphene nanosheet, the hexagonal boron nitride nanosheet and the molybdenum disulfide nanosheet have completely vertical overlapped areas. The flexible transistor has excellent bending performance and electrical performance, and when the curvature radius reaches 5 mm, the flexible transistor can also have the switch ratio as high as 8 orders of magnitude.

The invention belongs to the technical field of semiconductor photoelectric detection, and particularly relates to a self-powered photoelectric detector based on a Cs2CuBiI6 film and a preparation method of the self-powered photoelectric detector. The structure is composed of a glass substrate, a PEDOT: PSS conductive polymer layer, a Cs2CuBiI6 thin film layer, a PC61BM thin film layer, a BCP layer and a silver electrode. According to the technical scheme, the preparation of the lead-free Cs2CuBiI6 thin film is realized by adopting a simple preparation method, the defects of instability and lead toxicity of a traditional perovskite structure are overcome, and the prepared photoelectric detector has excellent photoelectric detection performance such as high response speed. And the method has very important significance in simplifying the perovskite light detector, simplifying the process, being environment-friendly and further enabling the perovskite light detector to be practical.

The invention belongs to the related technical field of semiconductor devices, and discloses an anisotropic dielectric layer transistor and a preparation method thereof. The transistor comprises a substrate, a grid electrode, a source electrode, a drain electrode, a conducting channel and a dielectric layer, the substrate serves as a carrier of the conducting channel, the dielectric layer is stacked above the conducting channel and coincides with the armchair crystal orientation of the conducting channel, the source electrode and the drain electrode are arranged on the two sides of the conducting channel, and the source electrode and the drain electrode are arranged on the substrate. The grid electrode is arranged on the dielectric layer, and the dielectric layer is of a low-symmetry crystal structure and is anisotropic in a horizontal plane. The invention further discloses a preparation method of the transistor. According to the invention, the leakage current is reduced, the electrical performance of the conducting channel is improved, the channel material is induced to generate obvious anisotropic electrical response, and the transistor shows better electrical performance.

The present invention discloses a photoelectric device having a perovskite coaxial heterogeneous one-dimensional nanowire array and a preparation method thereof. The photoelectric device comprises an electrode layer, a silicon dioxide substrate, and a perovskite coaxial heterogeneous one-dimensional nanowire array distributed on the silicon dioxide substrate; the perovskite coaxial heterogeneous one-dimensional nanowire is a core-shell structure; the core-shell structure has a molecular formula of A 1‑n B n The perovskite of CX3 is used as the core layer, with the molecular formula A 1‑n Cs n CY3 perovskite as shell; where 0≦n≦1, A is HC(NH2)2 + or CH3NH3 + , B is Cs + , C is Ge 2+ , Sn 2+ and Pb 2+ One of, X and Y are each independently one of Cl, Br and I, and X is different from Y. The optoelectronic device has a perovskite coaxial heterogeneous one-dimensional nanowire array, and its perovskite can form a heterojunction, which is beneficial to the transmission of electrons and holes, thereby improving the switching ratio and responsiveness of the optoelectronic device.

The invention provides a novel ferroelectric memory, and belongs to the technical field of semiconductors. The buffer layer is introduced between the source electrode and the channel layer to realize ohmic contact, and the tunneling layer is introduced between the drain electrode and the channel layer to realize tunneling contact. A buffer layer and a tunneling layer are respectively introduced between a source electrode and a channel layer and between a drain electrode and the channel layer of the ferroelectric memory, the novel ferroelectric memory is prepared, and a two-dimensional semiconductor / tunneling layer / metal tunnel junction is adopted as a channel. In the novel ferroelectric memory, the Fermi level of the two-dimensional semiconductor can be subjected to bipolar regulation and control through ferroelectric polarization, and regulation and control of the Fermi level can be sensitively detected through direct quantum tunneling current of a tunnel junction. A new hope is brought to logical devices, and a new solution is provided for high-density integration of the devices.

The application discloses a kind of phthalocyanine copper / inverted pyramid perovskite heterojunction photodetector and preparation method, comprising the following steps: 1) etching out the silicon piece with pyramid surface microstructure, as the base of growing perovskite single crystal;2) preparation perovskite solution, utilize silicon piece and glass piece as the frame of growth area restriction, utilize seed growth method, space limited method and inverse temperature crystallization method combined growth method preparation surface pyramid perovskite single crystal;3) utilize thermal evaporation in perovskite single crystal surface evaporation phthalocyanine copper film formation heterojunction, then utilize conductive carbon paste as upper and lower electrode preparation photodetector.The photodetector prepared by the application is stable at normal temperature and pressure, and has better photoelectric response relative to the control group device in a high humidity environment, and the device has good long-time humidity stability, which has guiding significance for the future high-performance photodetection field in high humidity environment such as sea, ship and island.

A single-phase oxide ferroelectric semiconductor thin film with low dark current and high UVC / UVA ratio, a preparation method and application in a self-powered solar blind detector belong to the technical field of semiconductor detectors.The single-phase oxide ferroelectric semiconductor thin film is composed of a ZnO thin film co-doped with Mg, Al and Li as an active absorption layer and a silicon substrate, is prepared through a co-doping strategy of Mg, Al and Li, and is applied in a solar blind detector through a matching electric field heat treatment process, so that the band gap of pure ZnO is effectively widened to the solar blind region, the built-in electric field generated by the donor-acceptor defect dipole constructed in the crystal lattice is utilized, and the high insulating state of the material is maintained through the charge compensation effect, so that the high-performance self-powered solar blind ultraviolet detection with low dark current, high responsivity and high on-off ratio is realized under zero applied bias.

The present invention provides a multifunctional device, including a substrate, a thin film electrode, quantum dot colloidal particles, and a metal electrode. The present invention obtains a multifunctional device by disconnecting a strip-shaped two-dimensional material film on a substrate, and reconnecting the disconnected film with colloidal quantum dots under the action of an external driving voltage, and finally forms a special planar structure of two-dimensional material film / quantum dots / two-dimensional material film. The multifunctional device provided by the present invention has functions similar to traditional photodiodes, and has good rectification characteristics and photoelectric detection performance. The difference between the multifunctional device provided by the present invention and traditional semiconductor photodiodes is that its performance is less affected by temperature and has a very high photoelectric response. At the same time, the preparation method of the multifunctional device provided by the present invention is simple in process, has no selection of substrates, and has a wide range of raw materials for two-dimensional material films and quantum dots, is easy to prepare, has low cost, is environmentally friendly, and is suitable for industrial production.

The present invention provides a p-type stannous oxide film, the p-type stannous oxide film comprises 19-26at% of tin oxide, 50-60at% of stannous oxide and 20-25at% of tin; and the p-type stannous oxide film is also doped with 2-10at% of tantalum. The present invention also provides a thin film transistor, the active layer of which is the p-type stannous oxide film as claimed in claim 1. The present invention also provides a method for preparing the thin film transistor, comprising the following steps: using a P-type Si substrate as a gate, thermally oxidizing the substrate, so that a SiO2 film as a gate dielectric layer grows on the surface of the P-type Si substrate; magnetron sputtering the surface of the SiO2 film so that the stannous oxide film as an active layer is deposited on the surface of the SiO2 film; annealing the stannous oxide film; thermally evaporating the annealed P-type Si substrate so that a gold film as a source and drain electrode is deposited on the surface of the stannous oxide film.

The invention relates to a phase change material which comprises an indium element and a sulfur element, the chemical formula of the phase change material is InxSy, x and y are atomic components of the elements, and 0 lt is met; x / (x + y) lt; 1, 0lt; y / (x + y) lt; 1; the invention also provides a phase change memory unit comprising the phase change material and a preparation method of the phase change memory unit. According to the InxSy phase change material, the resistance difference value before and after phase change is large, and very high adjustability is achieved; and when being applied to a phase change memory unit, the phase change memory unit has better data retention and higher operation speed.

The application discloses an application of a tripyridyl triazine zinc bromide complex in preparation of a photoelectric / radiation detector and belongs to the technical field of semiconductor photoelectric materials and devices. The application opens up a new use of a known material, the tripyridyl triazine zinc bromide complex, and realizes regulation of carrier transport performance by using free radicals generated by photoinduced electron transfer (PIET) in the ZnBr2(2-TPT) complex for the first time, breaks through the traditional cognition that the material is only used for optical discoloration, and successfully applies the material to the field of electrical detection. The photoelectric / radiation detector based on the tripyridyl triazine zinc bromide complex has high-performance detection performance: the detector prepared based on the ZnBr2(2-TPT) complex has extremely low dark current (originating from high resistance of the material in a dark state) and significant photocurrent response, realizes high on-off ratio and high sensitivity, and can effectively detect weak ultraviolet light and high-energy X rays.

The invention discloses a ferroelectric tunnel junction memory device, which comprises a first dielectric layer (100) and an array of field effect transistor monomers (1) arranged on the first dielectric layer in an array, the first dielectric layer (100) is sequentially provided with a drain electrode strip electrode (5), a second dielectric layer (200), a third dielectric layer (300), a ferroelectric tunnel junction first electrode (8), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction second electrode (10) and a fourth dielectric layer (400). And then the fourth dielectric layer (400) is used as the first dielectric layer (100) of the next device, and the operation is repeated, so that multi-layer stacking of the three-dimensional structure ferroelectric tunnel junction can be realized, and the device has the advantages of low power consumption, easiness in reading and high-density integration, and has good practicability.

The present application discloses a physical unclonable function structure based on ferroelectric transistors and a registration method and device, wherein the structure includes: an array circuit is an array structure formed by electrically connecting multiple ferroelectric transistor circuit structure units to form multiple rows and columns, the word lines of each row of circuit structure units are connected and connected to a decoding circuit, the bit lines of each column of circuit structure units are connected to a sensing line, and the bit lines are connected to a driving circuit, and the sensing lines are connected to a sensing circuit; the driving circuit is used to drive the word lines and bit lines of the array circuit; the decoding circuit is used to input a challenge signal and decode the input challenge signal into a corresponding address; the sensing circuit is used to generate an output response signal data from the input challenge signal by utilizing the random flipping characteristics of the polarization state of the ferroelectric transistors in the array circuit. The embodiments of the present application utilize the randomness and diversity of the polarization state of the ferroelectric transistor to realize a reconfigurable physical unclonable function, which has the advantage of low power consumption.

The present invention belongs to the field of semiconductor device technology, specifically a two-dimensional semiconductor transistor structure with controllable performance and a preparation method thereof. The present invention includes a substrate, a two-dimensional semiconductor material located on the substrate, a source-drain metal electrode, an oxide dielectric layer, and a laminated metal gate located on the dielectric layer; the oxide dielectric layer is a double-layer dielectric layer, and the laminated metal gate is a double-layer metal gate structure of a bottom active metal and a top inert metal. The present invention utilizes the solid-phase diffusion reaction that occurs when the bottom active metal directly contacts the oxide dielectric layer I to form a double-layer dielectric layer, and by controlling the thickness of the bottom active metal, the carrier concentration of the two-dimensional semiconductor material is precisely controlled by the electric dipole effect. The present invention can adjust the threshold voltage of the two-dimensional semiconductor field effect transistor, improve the switching ratio and on-state current of the device, and has broad application prospects in the manufacture of large-scale digital integrated circuits.

The present invention belongs to the field of semiconductor technology, and particularly relates to a photolithography method for source-drain electrodes and a method for preparing a thin film transistor. The photolithography method for source-drain electrodes provided by the present invention comprises the following steps: partially coating the surface of a patterned active layer, drying it, and obtaining a patterned active layer partially covered with photoresist; using the uncoated portion of the patterned active layer partially covered with photoresist, focusing the patterned active layer partially covered with photoresist on a photolithography mask for preparing source-drain electrodes, performing ultraviolet light exposure and growth, and forming source-drain electrodes on the surface of the patterned active layer. The present invention partially coats the patterned active layer with photoresist, and the portion not spin-coated with photoresist can be used as an alignment reference, so that the patterned active layer covered with photoresist is accurately focused on the channel position of the photolithography mask for preparing source-drain electrodes.

The present invention discloses a field effect tube and a manufacturing method thereof and a working method of the field effect tube, wherein the field effect tube comprises a field effect tube body, wherein the field effect tube body is formed of vanadium dioxide material and doped with hydrogen ions; a gate, wherein the gate is arranged on the upper end surface of the field effect tube body; a source and a drain, wherein the source is arranged on the first side of the field effect tube body, and the drain is arranged on the second side of the field effect tube body, wherein the second side is opposite to the first side. The field effect tube in the present invention has the advantages of higher switching ratio, faster switching speed and lower power consumption, which is conducive to promoting the development of semiconductor devices.