Two-dimensional semiconductor negative capacitance field-effect transistor and preparation method thereof

Abstract

The invention discloses a two-dimensional semiconductor negative capacitance field-effect transistor and a preparation method thereof. The device structure sequentially comprises a substrate, a two-dimensional semiconductor, a metal source-drain electrode, a ferroelectric gate medium with a negative capacitance effect and a metal gate electrode from bottom to top. The preparation method comprises the steps of firstly, preparing the transition metal chalcogenide two-dimensional conductor on a substrate; secondly, preparing the metal source-drain electrode by employing an electron beam lithography technology and combining a stripping process; thirdly, preparing a ferroelectric thin film with the negative capacitance effect on the structure; and finally, preparing the metal gate electrode on the thin film to form ferroelectric-controlled two-dimensional semiconductor negative capacitance field-effect transistor. Different from other two-dimensional semiconductor negative capacitance field-effect device structures, the metal-ferroelectric-semiconductor structure has the advantages that a high-performance negative capacitance field-effect device can be achieved; and an electrical test result shows that the subthreshold swing of the device is far smaller than 60mV / dec, the Boltzmann limit is broken through, and the two-dimensional semiconductor negative capacitance field-effect device simultaneously has the characteristics of extremely low power consumption, high-speed turnover and the like.

Description

technical field [0001] The invention relates to a low-power low-dimensional semiconductor electronic device, in particular to a two-dimensional semiconductor material negative capacitance field-effect transistor regulated and controlled based on a ferroelectric material and a preparation method thereof. Background technique [0002] With the development of integrated circuit technology, this technology has been widely used in various electronic products. Due to the continuous improvement of integration, while the performance of electronic products is improved, reducing power consumption is also an inevitable trend in the development of electronic products. Under the traction of Moore's Law, the size of traditional field effect transistor devices has been continuously reduced and the integration level has been continuously improved, resulting in an increase in chip power consumption. However, because the traditional field effect transistor is based on the hot carrier diffusio...

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Problems solved by technology

Although this type of device has achieved a small scale, the power consumption caused by high integration still cannot be solved, and the sub-threshold swing of the device still cannot exceed 60mV / dec, and it also faces the problem of mutual constraints of power consumption-performance-scale

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