45results about How to "Increase switching speed" patented technology

A transistor and a method of forming the same are disclosed. The method of forming the transistor comprises the steps of providing a semiconductor substrate consisting of a first region, a second region and a third region which are adjacent to one another; carrying out well region ion implantation, and forming a well region in the semiconductor substrate; carrying out channel ion implantation, and forming a first doped region in the surface of the well region in the first region; forming a gate structure on the semiconductor substrate and in the first region, the gate structure covering the first doped region in the first region; carrying out shallow doped ion implantation, forming a shallow doped source region in the semiconductor substrate and in the second region at one side of the gate structure, and forming a shallow doped drain region in the semiconductor substrate and in the third region at the other side of the gate structure; and forming an elevated source region on the shallow doped source region, and forming an elevated drain region on the shallow doped drain region. The method of the invention reduces the parasitic capacitance between the source and drain regions and the channel region and the substrate.

The invention discloses a manufacturing method of an integrated Schottky split-gate type power MOS device. The integrated Schottky split-gate type power MOS device is manufactured by utilizing 6 mask templates. Compared with a traditional manufacturing process of a split-gate type channel power MOS device, the manufacturing method of the integrated Schottky split-gate type power MOS device can reduce process steps and process difficulty.

The invention discloses a CMOS SOI radio frequency switching circuit. The CMOS SOI radio frequency switching circuit comprises a main NFET Stack, an auxiliary NFET Stack, a PFET Stack, a first capacitor and a second capacitor; grid electrodes of the main NFET Stack and the auxiliary NFET Stack are connected to a drain electrode and a source electrode of the PFET Stack step by step; one end of themain NFET Stack is connected to the auxiliary NFET Stack and the first capacitor, and the other end thereof is grounded; one end of the auxiliary NFET Stack is connected to the main NFET Stack and thesecond capacitor, and the other end thereof is grounded; the PFET Stack connection controls a second bias voltage; and the on-off state of the CMOS SOI radio frequency switching circuit is controlledby a first bias voltage and the second bias voltage. The CMOS SOI radio frequency switching circuit provided by the invention can increase the switching speed of a switch without reducing the grid capacitance of an NFET.

The invention aims to solve the problems that the thickness of single-layer metal of a metal composite material and the overall thickness of the metal composite material cannot be measured in the prior art. The invention provides a metal composite material ultrasonic thickness gauge capable of measuring the thickness of each layer of material of a metal composite material. The gauge comprises a voltage-adjustable power supply and an ultrasonic transmitting module, an ultrasonic receiving module, a data acquisition module and a data processing system, according to the metal composite material ultrasonic thickness gauge, the power supply supplies power to the ultrasonic transmitting module, the ultrasonic receiving module, the data acquisition module and the data processing system, the precision and the reliability can be ensured, and the thickness can still be accurately measured even under some poor coupling conditions.

The invention provides a semiconductor capable of improving the current rebounding phenomenon of a reverse-conducting double-insulated-gate bipolar transistor, improving the turn-off speed and improving voltage resistance. The semiconductor is structurally characterized in that a buried oxide is arranged on a P-type substrate and provided with a drift region, the drift region comprises a first N-type drift region, a first P-type drift region, a second N-type drift region and a second P-type drift region, the first N-type drift region and the first P-type drift region are arranged in an opposite-angle mode, and the second N-type drift region and the second P-type drift region are arranged in an opposite-angle mode; a P-type region is arranged in the first N-type drift region and the second P-type drift region, an N-type emitter region, a P-type collector region and cathode metal connecting the N-type emitter region with the P-type collector region are arranged in the P-type region, and a cathode gate oxide and a cathode polycrystalline silicon layer are arranged on the upper surface of the P-type region; an N-type region is arranged in the first P-type drift region and the second N-type drift region, an N-type collector region, a P-type emitter region and anode metal connecting the N-type collector region with the P-type emitter region are arranged in the N-type region, and an anode gate oxide and an anode polycrystalline silicon layer are arranged on the upper surface of the N-type region.

The invention relates to a transistor and a forming method thereof. The forming method of the transistor includes the following steps that: a semiconductor substrate including a first region, a second region, and a third region which are adjacent to one another is provided; well region ion implantation is performed, and a well region is formed in the semiconductor substrate; threshold voltage adjustment ion implantation is performed, so that g a first doped region can be formed at the surface of the well region in the second region; a gate structure is formed on the semiconductor substrate in the first region; shallow doping ion implantation is performed, so that a shallowly doped source region is formed in the semiconductor substrate at the second region at one side of the gate structure, and a shallowly doped drain region is formed in the semiconductor substrate at the third region at the other side of the gate structure; and a raised source region is formed on the shallowly doped source region, and a raised drain region is formed on the shallowly doped drain region. With the method of the present invention adopted, parasitic capacitance between the source region and a channel region, between the drain region and the channel region, between the source region and the substrate, as well as between the drain region and the substrate can be decreased.

The invention provides an OLED array substrate and a preparation method therefor and an OLED display apparatus. The OLED array substrate comprises a switching tube used for controlling pixel display, and a driving tube used for driving pixel display; the switching tube comprises a first insulating layer arranged between an active layer and a gate thereof; the driving tube comprises a second insulating layer arranged between an active layer and a gate thereof; and the dielectric constant of the first insulating layer is higher than that of the second insulating layer. By virtue of the OLED array substrate, the capacitance between the gate and the active layer of the switching tube can be improved relative to that of the driving tube, so that the sub threshold value swing of the switching tube is lowered relative to that of the driving tube, and the switching rate of the switching tube is further improved; and meanwhile, the capacitance between the gate and the active layer of the driving tube can be lowered relative to that of the switching tube, so that the voltage change of the driving tube is delayed, the sub threshold value swing of the driving tube is improved relative to that of the switching tube, and the gray scale display effect of the OLED display device is further reinforced.

The invention provides an optical communication device based on white light LED illumination. A communication function is achieved through an LED illuminating lamp array, cost is low, energy is saved, and the environment is protected. The optical communication device based on the white light LED illumination comprises a transmitting end and a receiving end, wherein the transmitting end comprises an LED modulation driving circuit connected with the LED illuminating lamp array, and the receiving end comprises an LED optical communication receiving circuit. The LED modulation driving circuit comprises a full-wave rectification bridge composed of four diodes capable of being connected into an alternating current power supply, the direct current voltage output end of the full-wave rectification bridge is connected with an energy-storage capacitor in parallel, the two ends of the energy-storage capacitor are connected with a filter circuit, the output end of the filter circuit is connected with a light modulation driving chip, a switch control pin of the chip is connected with the negative electrode of the LED illuminating lamp array, a switch pin of the chip is connected with the negative electrode of a voltage stabilizing diode and one end of an inductor, and the other end of the inductor is connected with the negative electrode of the LED illuminating lamp array and one end of a protective capacitor. The LED optical communication receiving circuit comprises a PIN photoelectric detector, an amplifying circuit and a signal processing unit.

The invention discloses a temperature control method and a temperature control device for an enrichment tube. In the method, when the temperature of the enrichment tube needs to be obtained, firstly, the platinum wire used as a heating element does not generate heat; The temperature value on the platinum wire serving as the temperature measuring element; then use the proportional integral differential algorithm to calculate the obtained temperature value on the platinum wire serving as the temperature measuring element and the temperature required by the enrichment tube to obtain the output control amount, when the output control When the output control value is less than or equal to 0, the platinum wire serving as the heating element will not generate heat until the next temperature control cycle begins; when the output control value is greater than 0, determine the heating power that needs to be loaded on the platinum wire as the heating element so The platinum wire that acts as a heating element heats the enrichment tube at this heating power until the next temperature control cycle begins; the advantage is that the platinum wire acts as both a temperature measuring element and a heating element, so there will be no Changing the temperature field near the temperature measurement point effectively improves the measurement accuracy.

The invention discloses a high-frequency harmonic parallel compensation device based on silicon carbide, and relates to the technical field of high-frequency harmonic parallel compensation. Accordingto the high-frequency harmonic parallel compensation device based on silicon carbide provided by the invention, a nonlinear load is simulated by a harmonic source to generate harmonic waves; a capacitor is arranged inside an active filter, the capacitor is serially connected between the active filter and a three-phase alternating current power grid, the voltage level on the output side of the active filter can be reduced effectively, and the active filter can be applied to a high-voltage network; simultaneously, the device is high in impedance for fundamental current and low in impedance for harmonic current; harmonic compensation current which can cancel out harmonic current component in load current in the harmonic waves generated by the harmonic source is generated by the active filter,so that the device solves the disadvantages that an existing active filter mainly uses an IGBT switch device, the compensation ability of the active filter for high-frequency harmonic waves is subjected to the switching frequency of IGBT and the high-frequency harmonic waves cannot be compensated effectively.

The invention discloses a combined switch. The combined switch comprises a junction field effect transistor and a diode. The junction field effect transistor comprises a gate electrode, a source electrode and a drain electrode; the diode comprises an anode and a cathode; the drain electrode of the junction field effect transistor is a first terminal of the combined switch; the source electrode ofthe junction field effect transistor is connected with the cathode of the diode; the gate electrode of the junction field effect transistor is connected with the anode of the diode; and the anode of the diode is a second terminal of the combined switch. Compared to a single diode, the combined switch disclosed by the invention has a higher reverse withstand voltage, and has zero reverse recovery characteristic and a lower forward turn-on voltage.

The invention discloses a gallium-nitride-based inverter chip and a forming method therefor, and the chip comprises a substrate; a gallium nitride channel layer located on the substrate; a barrier layer located on the gallium nitride channel layer; a P-type III-family metal nitride layer located on the surface of the barrier layer; a first electrode located on the surface of the P-type III-family metal nitride layer; a second electrode, a third electrode and a fourth electrode, which are all located on the surface of the barrier layer. The chip is good in transmission performance, and is strong in loading capability.

The invention discloses a two-dimensional negative quantum capacitance transistor device and a preparation method thereof. The two-dimensional negative quantum capacitance transistor device comprises a substrate; a buried gate which is formed in the substrate, wherein the upper surface of the buried gate is flush with the upper surface of the substrate; a third-generation topological insulator layer which is formed on the buried gate, wherein the length of the third-generation topological insulator layer is equal to that of the buried gate; a high-K dielectric layer which covers the third-generation topological insulator layer; a two-dimensional channel layer which is formed on the high-K dielectric layer, wherein the two-dimensional channel layer and the third-generation topological insulator layer have a common area; a source electrode and a drain electrode which are formed on the substrate and the two sides of the two-dimensional channel layer respectively, partially cover the two-dimensional channel layer and are not overlapped with the buried gate, wherein the topological insulator layer provides negative quantum capacitance, so the total capacitance of the gate is increased, and the sub-threshold swing is reduced.

The invention relates to a silicon carbide power semiconductor device and a field effect transistor. The silicon carbide power semiconductor device comprises a substrate and a plurality of grid electrode grooves arranged at intervals, the plurality of spaced grid electrode grooves are formed at one side of the substrate, and a first grid electrode and a second grid electrode are arranged in each grid electrode groove. The first grid electrode and the second grid electrode are arranged along the extending direction of the substrate, the first grid electrode is of a first conductivity type. and the second grid electrode is of a second conductive type. A grid electrode oxide layer is formed on the inner wall of each grid electrode groove, and is located between the inner wall of the grid electrode groove and the first grid electrode and the second grid electrode. After the first grid electrode and the second grid electrode form a PN junction, the second grid electrode is completely exhausted by the first grid electrode, and a space charge region is formed. The space charge region can bear voltage, equivalently, the thickness of the grid electrode oxide layer is increased, and with the increase of the thickness of the grid electrode oxide layer, the capacitance between the grid electrode and a shielding region is reduced, so that the grid charge is further reduced, the switching rate can be improved, and the switching loss is reduced.

The invention relates to an operation order management system comprising a data module unit, a project management module unit, a task management module unit, a rehearsal module unit, a video module unit, a log management module unit and a human-computer interface unit. The data module unit, the project management module unit, the task management module unit, the rehearsal module unit, the video module unit, the log management module unit and the human-computer interface unit are application units installed in a switch cabinet switching control system of an electric power management department.According to the invention, the whole process of writing, approving and executing the operation order is intelligently controlled, and the work of related personnel is standardized. Error caused by personnel negligence is avoided, and the order making accuracy and efficiency of the operation order are improved. Compared with manual switching, the switching speed is improved, and the task accuracyand safety are improved. In actual operation, intelligent monitoring can be carried out on the electric operating mechanisms of multiple switch cabinets, and switching of the electric operating mechanisms is automatically controlled on the basis of operation order specifications.

The invention discloses a 600MW unit circulating water energy-saving optimization operation prompting method. According to the method, through designing a data acquisition model, data acquisition is carried out on circulating water temperature, unit load and condenser vacuum degree, a data sample library is established, and collected data are uploaded to the data sample library; the contents in the data sample library are screened, sorted and stored, and the running state of the unit is monitored in real time; circulating water optimization operation technical measures are judged through the prompt logic, the circulating water optimization operation mode is given in combination with the operation working condition, the state and the performance of a circulating water pump are monitored, operation personnel can be prompted to adjust in time, and the problems that the energy consumption of the unit is increased as existing circulating pump operation optimization measures are not timely executed and the energy waste is caused as circulating switching is not timely are solved.