20results about How to "Increased current capability" patented technology

The utility model relates to a laminated busbar packaging module with pins at the top, which is characterized in that on the basis of division of a power area and a non-power area of a wiring layer on a substrate (1), copper bars with pins at the top are applied to the power area to form power pins, and an independent copper bar structure and a laminated copper bar structure are specifically designed; according to the laminated busbar packaging module, the Pins (5) with the top pins are applied in the non-power area to form all the signal pins, the designed laminated busbar packaging module has the advantages of being low in parasitism, higher in efficiency and higher in current capacity, and in practical application, heat dissipation is better, reliability is better, and assembling is easier.

The invention discloses a wide bandgap power diode with a periodic composite anode, which comprises a wide bandgap semiconductor material substrate layer, a third anode groove, a wide bandgap semiconductor material epitaxial layer, and a periodic first anode groove and a periodic second anode on the wide bandgap semiconductor material epitaxial layer from bottom to top, a first dielectric layer and a second dielectric layer are sequentially arranged on the upper surfaces of the first anode groove and the wide bandgap semiconductor material epitaxial layer, a second dielectric layer is arranged on the upper surfaces of the second anode groove and the wide bandgap semiconductor material epitaxial layer, and a third dielectric layer is arranged on the third anode groove. And a metal anode and a metal cathode are respectively arranged on the upper surface of the wide bandgap semiconductor material epitaxial layer and the lower surface of the wide bandgap semiconductor material substrate layer. Benefited from the periodic composite anode structure, the device has the performance advantages of high current density, high breakdown voltage, low on-resistance and low reverse electric leakage.

The utility model provides an asymmetric high-reliability trench gate silicon carbide VDMOS. The asymmetric high-reliability trench gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; the P-type well region is connected to the drift layer; the shunt region is connected to the drift layer and located at the lower left corner of the first groove, and the P-type base region is connected to the shunt region and located at the left side of the first groove; the P-type source region is connected to the P-type well region; the N-type source region is respectively connected with the P-type well region, the P-type base region and the P-type source region; the Schottky metal layer is connected to the drift layer, the P-type well region and the N-type source region; the outer side surface of the insulating dielectric layer is respectively connected with a P-type source region, an N-type source region, a P-type well region, a P-type base region and a shunt region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type source region, the N-type source region and the Schottky metal layer; the drain metal layer is connected to the silicon carbide substrate, so that the characteristics of the device after conduction are ensured at one side, the follow current characteristics of the diode of the device body are ensured at one side, and the reliability of the device is improved.

The disclosure provides a low dropout linear regulator circuit and a memory, the circuit comprising: a first transistor, a second transistor and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold; the first end of the first transistor and the second end of the second transistor are connected to receive a power supply voltage; the second end of the first transistor and the first end of the second transistor are connected to output a target voltage; the control end of the second transistor receives a power-on control signal, and the second transistor is used to output the target voltage during the power-on process; the feedback control circuit is connected with the control end of the first transistor, the feedback control circuit is used to receive the power-on control signal, control the first transistor to be disconnected during the power-on process, and control the first transistor to output the target voltage after the power-on is completed; wherein the power-on control signal is in an enabled state during the power-on process, and is in a disabled state during the remaining period. The disclosure can reduce the circuit area, avoid overvoltage and simplify the timing.

The invention provides a BCD device and a preparation method thereof, the BCD device comprises a substrate, an epitaxial layer, a super junction VDMOS unit and a plurality of planar transistor units, the epitaxial layer is located on a first surface of the substrate, the epitaxial layer is internally provided with a first region and at least one second region, and the second region is internally provided with at least one first medium voltage well; the super-junction VDMOS unit comprises at least two second medium-voltage traps and a back metal layer, the second medium-voltage traps are transversely arranged in the first region at intervals, and the back metal layer is located on the second surface of the substrate and electrically connected with the substrate; part of composition structures of the planar transistor units are located in the first medium-voltage traps in the corresponding second regions. The super-junction VDMOS unit is integrated in the BCD device, compared with a conventional LDMOS unit, the super-junction VDMOS unit has better current capacity, smaller area occupation and higher reliability, the performance and reliability of the BCD device are improved, the first medium-voltage well and the second medium-voltage well are prepared synchronously, and the BCD device has the advantages of being simple in manufacturing method, low in cost, high in reliability and the like.

The invention discloses an active inductor for carrier communication of a direct-current power supply, which is an integrated circuit and comprises a first-stage circuit, a second-stage circuit, a third-stage circuit and a fourth-stage circuit, the first-stage circuit comprises a floating-end active inductor L1 and a grounding-end active inductor L2, and two ends of the L1 are correspondingly connected with a VP and a VOP, so that a rectified positive signal alternating-current part is blocked, and a positive direct-current signal Iin is reserved; the two ends of the L2 are correspondingly connected with the VN and the VON, so that the alternating current part of the rectified negative signal is blocked, and a negative direct current signal-Iin is reserved; a voltage sampling part of the second-stage circuit L2, a third-stage circuit is a carrier communication bus signal + / -V low-level period detection part, a fourth-stage circuit is a low-level conduction part, and a bus signal + / -V is compared with a reference voltage VREF so as to control the sampling voltage to drive the fourth-stage circuit to be switched on or switched off. According to the invention, integration in a chip is realized, and advantages of low conduction voltage drop, large equivalent inductance and the like are realized.

This invention discloses a high-voltage LDMOS device, wherein a first field plate dielectric layer is provided on a first-doped substrate / first-doped epitaxial layer, and only in the second-doped LDMOS device region, the first field plate dielectric layer being a partial LOCOS structure; a first and second-doped drift region is provided below the first field plate dielectric layer in the first-doped substrate / first-doped epitaxial layer; a second and second-doped drift region is provided below the first and second-doped drift regions in the first-doped substrate / first-doped epitaxial layer; a second field plate dielectric layer is provided on the side of the first field plate dielectric layer near the channel, the second field plate dielectric layer being constructed by filling the dielectric layer using a shallow trench isolation process; the device drain is connected to the first and second-doped drift regions and the second and second-doped drift region and the second-doped heavily doped region through a second-doped well implantation. This invention reduces specific on-resistance while ensuring high breakdown voltage, improving process compatibility and device performance.

The invention relates to a SiC trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) super junction for enhancing reverse recovery performance and a preparation method of the SiC trench MOSFET super junction, and the SiC trench MOSFET super junction comprises a drain electrode, an n + substrate, an n-type drift region and two source electrodes which are bilaterally symmetrical, the left end and the right end of the n-column region respectively comprise a p1 + base region, a high-concentration first n + source region and a super junction region formed by a low-concentration n1 + region, the p1 + base regions are in bilateral symmetry, the p + source regions are in bilateral symmetry, the p body region is in bilateral symmetry, and the second n + source region is in bilateral symmetry. The n column region, the p + shielding region, the p body region and the second n + source region jointly form a groove, a gate oxide layer is arranged on the groove, and gate metal is arranged on the gate oxide layer; the sources are located at the left and right ends of the gate oxide layer respectively. According to the invention, the reverse recovery capability is strong, the voltage resistance is improved, the parasitic capacitance is reduced, the switching speed is improved, and the on-resistance is reduced.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

According to the ESD protection circuit provided by the utility model, the state switching circuit is arranged at the input end, and whether a core circuit is in a power-on state or not is judged by detecting the output voltage of the power management circuit in the chip, namely whether voltage exists at the second signal end VDD or not. The ESD detection circuit is controlled through the output voltage of the state switching circuit, so that the ESD detection circuit does not work after a chip is powered on, and the false triggering problem of the ESD control circuit is eliminated from the source; when the core circuit is in a non-power-on state, the detection circuit detects the second signal end, if a transient change second signal, namely an ESD signal, is detected, a control signal is output and transmitted to the first control circuit through the voltage following circuit, and an input signal of the first control circuit changes along with an input signal of the voltage following circuit. The first control circuit is started to form an ESD discharge path with the voltage follower circuit, a channel of a key device of the core circuit is controlled to be closed, and meanwhile, a first signal end is closed to protect the core circuit, so that the anti-ESD capability of the core circuit is enhanced.

The utility model discloses a magnetorheological fluid damping component and vibratory hammer, the magnetorheological fluid damping component comprises a damping piece, sealing pieces, magnetorheological fluid and an electromagnetic component, the damping piece is provided with a containing hole, the sealing pieces are arranged at the two ends of the containing hole so as to cooperate with the containing hole to form a sealed space, the electromagnetic component is arranged in the containing hole, and the magnetorheological fluid is arranged in the containing hole. The containing hole is configured to contain the magnetorheological fluid and the electromagnetic assembly, and the electromagnetic assembly is configured to change the magnetic field of the electromagnetic assembly through current so as to adjust the viscosity of the magnetorheological fluid and further adjust the damping force of the magnetorheological fluid damping assembly. According to the magnetorheological fluid damping assembly, the viscosity of the magnetorheological fluid is adjusted by changing the magnetic field, then damping force adjustment of the magnetorheological fluid damping assembly is achieved, and the magnetorheological fluid damping assembly has the advantage of automatically adjusting the damping force of the damping assembly.

The utility model belongs to but is not limited to IPM technical field, especially intelligent IPM power module device, intelligent IPM power module device includes lead frame, and lead frame includes multiple base island, multiple pin, high voltage pin VBw, VBv, VBu set up in one side of lead frame, and low voltage pin is symmetrically set up in the other side of lead frame, the other side of lead frame still is provided with overtemperature protection pin and overcurrent protection pin, the utility model discloses high voltage pin and low voltage pin separate two sides, avoid high voltage and low voltage pin in the same side, improve the module volume owing to the insulation electrical clearance, under the same volume, the utility model increases overtemperature, overcurrent protection function.

This invention provides a bidirectional SCR electrostatic discharge (ESD) protection device, comprising a P-type substrate, an N-type buried layer, a P-type epitaxial layer, a deep N-type well, a first P-type well, a second P-type well, an N-type well, a high-voltage N-type well, heavily doped P-type material, a first shallow trench isolation layer, heavily doped N-type material, a first field oxygen isolation layer, and a floating field plate. The P-type substrate is located at the bottom layer, and the N-type buried layer is located above the P-type substrate, with their surfaces flush. The P-type epitaxial layer is located above the P-type substrate. The deep N-type well, the first P-type well, the second P-type well, the N-type well, the high-voltage N-type well, the heavily doped P-type material, and the heavily doped N-type material are all formed within the P-type epitaxial layer via ion implantation. This invention reduces the device's turn-on voltage through the floating field plate, and achieves sequential or simultaneous turn-on of different current discharge paths through two current discharge paths and the length of the field oxygen isolation layer, controlling the device's double hysteresis characteristics to avoid latch-up effects. The centrosymmetric structure increases the longitudinal current, improving the overall current capability of the device.

The invention discloses a lateral double-diffused metal oxide field effect transistor with a coherent P-Top layer. The two ends of the longitudinal P-type injection layer section are located below the first shallow trench isolation region and the second shallow trench isolation region respectively, the coherent P-type injection layer is formed in the mode that the longitudinal P-type injection layer section is connected with the transverse P-type injection layer section, and doping optimization introduced by the low-resistance path region and the STI region on the surface of the device is coherent into a whole. Therefore, the electric field distribution of the low-resistance path region and the STI region is adjusted together, and the local electric field intensity in the drift region of the device is reduced. According to the LDMOS device, the current performance is improved by reducing the longitudinal width of the P-Top layer between the first shallow trench isolation region and the second shallow trench isolation region, so that the performance of the LDMOS device is realized. According to the invention, the coherent P-Top layer is arranged in the low-resistance path region, and the STI region is optimized, so that the breakdown performance is improved, and the electric field control capability and the performance of the device are improved.

The utility model belongs to the technical field of semiconductor devices, and discloses a semiconductor device with a multi-channel structure, which comprises a substrate, a buffer layer, a channel layer, a barrier layer and the multi-channel structure, the buffer layer, the channel layers and the barrier layers are sequentially arranged on one side of the substrate in the first direction, the multiple barrier layers and the multiple channel layers are arranged, and the multiple barrier layers and the multiple channel layers are arranged in a staggered mode in the first direction; the first direction is perpendicular to the plane where the substrate is located and points to the barrier layer from the substrate; the multi-channel structure comprises a plurality of 2DEG channels arranged along a first direction, the plurality of 2DEG channels are arranged side by side along a second direction, and the plurality of 2DEG channels are used for each barrier layer to convey electrons; the second direction is perpendicular to the plane where the substrate is located and points to the other opposite end from one end of the substrate. According to the invention, large current can be obtained, the problem of large current concentration can be effectively relieved, and the semiconductor device is prevented from being burnt and failed due to overlarge current.

A substrate (1) for a power module (30) comprises a lower portion (10) and an upper portion (20). The lower portion (10) comprises a cooling structure (11) configured to contact the coolant during operation of the power module (30). The upper portion (20) is coupled to the lower portion (10). The cooling structure (11) faces away from the upper portion (20) and comprises a surface (12) having a given surface structure (13, 14) comprising Regt; and at least one of a plurality of protrusions having a respective height (H) of 2 [mu] m or more with respect to a surface normal (A) perpendicular to the surface (12) of the cooling structure (11), and an average roughness.

The invention discloses a low-on-resistance high-voltage SOI LDMOS power device and a preparation method thereof.The power device comprises a P-type substrate, a BOX layer, a P-Window buried layer, a first N-type drift region, a second N-type drift region, a first P-pillar buried layer and a second P-pillar buried layer, the P-Window buried layer and the BOX layer are arranged on the upper surface of the P-type substrate in the left-right direction, and the first N-type drift region and the second N-type drift region are arranged on the lower surface of the P-type substrate in the left-right direction. The N-type drift region I and the N-type drift region II are respectively overlapped above the P-Window buried layer and the BOX layer, an oxidation tank is arranged on the left side of the N-type drift region I, polycrystalline silicon grows in the oxidation tank, the P-pillar buried layer I and the P-pillar buried layer II are arranged along the vertical direction and extend rightwards from the left side surface of the N-type drift region I into the N-type drift region II, and the P-pillar buried layer II and the P-pillar buried layer II are arranged along the vertical direction. The length of the first P-pillar buried layer is larger than that of the second P-pillar buried layer, and the doping concentration of the first N-type drift region and the doping concentration of the second N-type drift region are different. According to the device structure, the on resistance is effectively reduced, the breakdown voltage is improved, and the performance of the device is well improved.

The present application relates to the technical field of multi-distributed power supply system control, and particularly relates to a nonlinear variable structure observer robust control device and control method for a multi-source power supply system.The present application comprises a plurality of distributed power sources, a power converter, a common bus, a current sensor, a voltage sensor, a nonlinear variable structure observer, a power distribution controller, a voltage controller, and a current controller.The power distribution controller adopts a voltage and current deviation longitudinal intercept double compensation algorithm based on proportional integral differential control of average voltage and current.The voltage controller adopts a nonsingular exponential voltage variable structure control algorithm.The current controller adopts a nonsingular exponential current variable structure control algorithm.The present application provides accurate parameters for the distributed controller, helps the system to resist noise and uncertain interference, and improves the performance of the system and the robustness of the bus voltage.

The present invention discloses a lateral double diffused metal oxide field effect transistor with a continuous P-Top layer. The present invention adopts a longitudinal P-type injection layer segment, the two ends of which are respectively located below a first shallow trench isolation region and a second shallow trench isolation region, and forms a continuous P-type injection layer by connecting the longitudinal P-type injection layer segment with the lateral P-type injection layer segment, and optimizes the doping introduced into the low-resistance path region and the STI region on the surface of the device to be continuous as a whole, thereby adjusting the electric field distribution of the low-resistance path region and the STI region together, and reducing the local electric field strength in the drift region of the device. The present invention improves the current performance by reducing the longitudinal width of the P-Top layer located between the first and second shallow trench isolation regions, thereby achieving the performance of the LDMOS device. The present invention adopts a continuous P-Top layer placed in the low-resistance path region, and improves the breakdown performance by optimizing the STI region, thereby improving the electric field control capability and device performance of the device.

The utility model relates to a heating module for brazing equipment, in particular to reflow brazing equipment or selective brazing equipment. The fan impeller can be driven by the motor; a module controller; the module controller is arranged in or on the heating module and is arranged in such a way that a control current for controlling and / or regulating the rotational speed of the electric machine and / or the heating temperature of the heating element is generated in dependence on control data and / or temperature data; and wherein the module controller has a communication interface, which is arranged in such a way that it receives the control data and / or temperature data from a controller of the brazing device. The utility model also relates to a module controller for the heating module, a brazing device comprising the heating module and a controller for controlling the brazing device.