5results about How to "Increased current capability" patented technology

The utility model provides an asymmetric high-reliability trench gate silicon carbide VDMOS. The asymmetric high-reliability trench gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; the P-type well region is connected to the drift layer; the shunt region is connected to the drift layer and located at the lower left corner of the first groove, and the P-type base region is connected to the shunt region and located at the left side of the first groove; the P-type source region is connected to the P-type well region; the N-type source region is respectively connected with the P-type well region, the P-type base region and the P-type source region; the Schottky metal layer is connected to the drift layer, the P-type well region and the N-type source region; the outer side surface of the insulating dielectric layer is respectively connected with a P-type source region, an N-type source region, a P-type well region, a P-type base region and a shunt region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type source region, the N-type source region and the Schottky metal layer; the drain metal layer is connected to the silicon carbide substrate, so that the characteristics of the device after conduction are ensured at one side, the follow current characteristics of the diode of the device body are ensured at one side, and the reliability of the device is improved.

The disclosure provides a low dropout linear regulator circuit and a memory, the circuit comprising: a first transistor, a second transistor and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold; the first end of the first transistor and the second end of the second transistor are connected to receive a power supply voltage; the second end of the first transistor and the first end of the second transistor are connected to output a target voltage; the control end of the second transistor receives a power-on control signal, and the second transistor is used to output the target voltage during the power-on process; the feedback control circuit is connected with the control end of the first transistor, the feedback control circuit is used to receive the power-on control signal, control the first transistor to be disconnected during the power-on process, and control the first transistor to output the target voltage after the power-on is completed; wherein the power-on control signal is in an enabled state during the power-on process, and is in a disabled state during the remaining period. The disclosure can reduce the circuit area, avoid overvoltage and simplify the timing.

This invention discloses a high-voltage LDMOS device, wherein a first field plate dielectric layer is provided on a first-doped substrate / first-doped epitaxial layer, and only in the second-doped LDMOS device region, the first field plate dielectric layer being a partial LOCOS structure; a first and second-doped drift region is provided below the first field plate dielectric layer in the first-doped substrate / first-doped epitaxial layer; a second and second-doped drift region is provided below the first and second-doped drift regions in the first-doped substrate / first-doped epitaxial layer; a second field plate dielectric layer is provided on the side of the first field plate dielectric layer near the channel, the second field plate dielectric layer being constructed by filling the dielectric layer using a shallow trench isolation process; the device drain is connected to the first and second-doped drift regions and the second and second-doped drift region and the second-doped heavily doped region through a second-doped well implantation. This invention reduces specific on-resistance while ensuring high breakdown voltage, improving process compatibility and device performance.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

This invention provides a bidirectional SCR electrostatic discharge (ESD) protection device, comprising a P-type substrate, an N-type buried layer, a P-type epitaxial layer, a deep N-type well, a first P-type well, a second P-type well, an N-type well, a high-voltage N-type well, heavily doped P-type material, a first shallow trench isolation layer, heavily doped N-type material, a first field oxygen isolation layer, and a floating field plate. The P-type substrate is located at the bottom layer, and the N-type buried layer is located above the P-type substrate, with their surfaces flush. The P-type epitaxial layer is located above the P-type substrate. The deep N-type well, the first P-type well, the second P-type well, the N-type well, the high-voltage N-type well, the heavily doped P-type material, and the heavily doped N-type material are all formed within the P-type epitaxial layer via ion implantation. This invention reduces the device's turn-on voltage through the floating field plate, and achieves sequential or simultaneous turn-on of different current discharge paths through two current discharge paths and the length of the field oxygen isolation layer, controlling the device's double hysteresis characteristics to avoid latch-up effects. The centrosymmetric structure increases the longitudinal current, improving the overall current capability of the device.