3results about How to "Increased current capability" patented technology

The disclosure provides a low dropout linear regulator circuit and a memory, the circuit comprising: a first transistor, a second transistor and a feedback control circuit; the gate dielectric layer thickness of the first transistor is less than a preset threshold; the first end of the first transistor and the second end of the second transistor are connected to receive a power supply voltage; the second end of the first transistor and the first end of the second transistor are connected to output a target voltage; the control end of the second transistor receives a power-on control signal, and the second transistor is used to output the target voltage during the power-on process; the feedback control circuit is connected with the control end of the first transistor, the feedback control circuit is used to receive the power-on control signal, control the first transistor to be disconnected during the power-on process, and control the first transistor to output the target voltage after the power-on is completed; wherein the power-on control signal is in an enabled state during the power-on process, and is in a disabled state during the remaining period. The disclosure can reduce the circuit area, avoid overvoltage and simplify the timing.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

This invention provides a bidirectional SCR electrostatic discharge (ESD) protection device, comprising a P-type substrate, an N-type buried layer, a P-type epitaxial layer, a deep N-type well, a first P-type well, a second P-type well, an N-type well, a high-voltage N-type well, heavily doped P-type material, a first shallow trench isolation layer, heavily doped N-type material, a first field oxygen isolation layer, and a floating field plate. The P-type substrate is located at the bottom layer, and the N-type buried layer is located above the P-type substrate, with their surfaces flush. The P-type epitaxial layer is located above the P-type substrate. The deep N-type well, the first P-type well, the second P-type well, the N-type well, the high-voltage N-type well, the heavily doped P-type material, and the heavily doped N-type material are all formed within the P-type epitaxial layer via ion implantation. This invention reduces the device's turn-on voltage through the floating field plate, and achieves sequential or simultaneous turn-on of different current discharge paths through two current discharge paths and the length of the field oxygen isolation layer, controlling the device's double hysteresis characteristics to avoid latch-up effects. The centrosymmetric structure increases the longitudinal current, improving the overall current capability of the device.