Double-gate SOI-LIGBT device with P-type buried layer

Abstract

The invention relates to a semiconductor device and discloses a double-gate SOI-LIGBT device with a P-type buried layer. Under the condition that voltage resistance is ensured, the current capacity of the device is enhanced. According to the double-gate SOI-LIGBT device, the P-type buried layer is additionally arranged, traditional bulk silicon is changed into polycrystalline silicon for serving as filling materials of a separation groove, the separation groove is connected with a gate end electrode through a metal structure and accordingly serves as a gate electrode in the lateral direction of the device. The double-gate SOI-LIGBT device not only can serve as a gate field plate to be shrunk into an electric field near a channel region for meeting the voltage resistance requirement. Meanwhile, the double-gate SOI-LIGBT device can serve as a longitudinal gate electrode so that the current can stream on the surface and can also stream below the P-type buried layer in a device body area, the current capacity is enhanced, on-resistance is reduced, and therefore the size of the device in the width direction can be shortened under the condition that the voltage resistance is ensured. The double-gate SOI-LIGBT device with the P-type buried layer is suitable for a PDP scanning driving chip.

Description

Technical field [0001] The invention relates to a semiconductor device, in particular to a novel dual-gate SOI-LIGBT (Silicon-on-Insulator-Horizontal Insulated Gate Transistor) device with a P-type buried layer used in a PDP scan drive chip. Background technique [0002] Plasma displays have been widely used due to their wide color gamut and fast dynamic response. Among them, the line scan driver chip is used for the horizontal line scan of the display and is a key component of the plasma display. In the design of the line scan driver chip, it is necessary to output 96 channels of independent high voltage. The output stage includes a pull-up transistor and a pull-down transistor. The current capability of the pull-down transistor needs to reach 1.5A and the off-state withstand voltage is 200V, so the width of the transistor is relatively large, 96 channels The total area of ​​the pull-down LIGBT (lateral insulated gate transistor) reaches 30% of the overall chip area. [0003] Th...

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Problems solved by technology

[0005] In order to achieve high integration of the chip, it is a good solution to further reduce the area of ​​the chip and minimize the size of the SOI-LIGBT device in the width direction. However, at present, it is necessary to further reduce the device under the condition of ensuring its withstand voltage The size in the width direction can only be achieved by increasing the current capability of the device, and there is no good solution yet.

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