25results about How to "Improve switching characteristics" patented technology

The invention discloses a tunneling gate HEMT device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a transition layer, a buffer layer, a channel layer and a barrier layer, wherein the transition layer, the buffer layer, the channel layer and the barrier layer are sequentially located on the substrate layer; the p-GaN layer is located on the barrier layer; the isolation structure is located on the side wall of the HEMT device, and the isolation structure penetrates through the barrier layer and the channel layer and is located on the buffer layer; the passivation layer is located on the side wall of the p-GaN layer and on the barrier layer; the tunneling layer is positioned at the bottom and the side part of the grid opening area of the passivation layer; the grid electrode penetrates through the passivation layer and is positioned on the tunneling layer; and the source electrode and the drain electrode are respectively located at different sides of the p-GaN layer, and the source electrode and the drain electrode respectively penetrate through the passivation layer and are located on the barrier layer. Compared with the prior art, a layer of thin medium is deposited in the groove of the grid electrode to serve as the tunneling layer, so that the breakdown voltage of the grid electrode of the HEMT device is effectively improved.

The invention relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with fast recovery and low power consumption characteristics, and belongs to the technical field of semiconductors. The device includes: a drain metal contact; the substrate is formed on the contact surface of the drain electrode metal; the drift region is formed on the surface of the substrate; the NCSL is formed on the surface of the drift region; the first Pbase is formed on the surface of the NCSL; the first source region is formed on the surface of the first Pbase; the second Pwell is formed on the surface of the drift region; the second P + region is formed on the surface of the second Pwell; the first P-well is formed on the surface of the drift region; the first P + region is formed on the surface of the first Pwell; the MOS channel diode is formed on the surface of the second P-well; the L-shaped split gate is formed on the surfaces of the MOS channel diode and the NCSL; and a source metal contact formed on the top of the device.

The invention discloses a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode, which comprises a drain metal layer, a silicon carbide N-type doped substrate, a silicon carbide N-type epitaxial region and a silicon carbide N-type current expansion layer which are sequentially arranged from bottom to top, and is characterized in that a silicon carbide P-type buried layer is embedded in the middle of the silicon carbide N-type current expansion layer; groove gate oxide layers are arranged at the two ends of the silicon carbide N-type current expansion layer respectively, a silicon carbide P-type shielding layer is arranged at the bottom of each groove gate oxide layer, silicon carbide P-type base regions are arranged at the two ends of the upper side of the silicon carbide N-type current expansion layer respectively, and a silicon carbide N-type source region and a silicon carbide P-type source region are arranged above each silicon carbide P-type base region at the same time. And a heterojunction polycrystalline silicon region is arranged in the center of the top of the silicon carbide N-type current expansion layer. The invention further discloses a manufacturing method of the silicon carbide MOSFET integrated with the heterojunction diode, the device has low reverse turn-on voltage, and the static quality factor and the short circuit reliability of the device are improved.

The invention relates to the technical field of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) performance optimization, and discloses a high-performance silicon carbide MOSFET switching characteristic optimization method and device.According to the method, data acquisition of working parameters is carried out on an MOSFET switch, working monitoring data is obtained, parameter data acquisition is carried out on a voltage driving unit and a resistance adjusting unit, and voltage driving data and resistance adjusting data are obtained; analyzing the working state of the switch according to the collected data to obtain working state characteristics, performing gradient analysis based on the working state characteristics, formulating a plurality of optimization test schemes, sequentially executing the optimization test schemes of each gradient, obtaining optimization test characteristics, and determining whether to execute the optimization scheme of the next gradient or not according to the test characteristics. Through the method, the switching characteristics of the silicon carbide MOSFET can be systematically and accurately optimized. The optimization efficiency is improved by the real-time data analysis and gradient optimization steps, the trial and error cost is reduced, and the performance stability and reliability of the MOSFET are enhanced.

The invention provides a silicon carbide floating junction structure for improving switching characteristics along a slope terminal P channel, and relates to the technical field of semiconductor power devices. Comprising an N-type drift region formed on an N-type substrate; the plurality of first P-type floating junctions, the plurality of second P-type floating junctions and the plurality of P-type doped regions are all formed in the middle region of the N-type drift region, are arranged at intervals and are respectively and oppositely arranged up and down; the first P-type floating junction transition region is formed in the N-type drift region and surrounds the plurality of first P-type floating junctions; the second P-type floating junction transition region is formed in the N-type drift region and surrounds the plurality of second P-type floating junctions; the P-type transition region is formed in the N-type drift region and surrounds the plurality of P-type doped regions; and the inclined plane terminal P channels are formed on inclined planes at two ends of the N-type drift region, inclined planes at two ends of the first P-type floating junction transition region, inclined planes at two ends of the second P-type floating junction transition region and two ends of the P-type transition region. Therefore, the switching characteristic is relatively good, the process cost is relatively low, and the time cost is relatively low.

The utility model discloses a jacquard device and a driving circuit for the same. The driving circuit comprises a power supply VCC1, a power supply VCC2, a resistor R1, a resistor R3, a triode Q1, a triode Q2, a diode D1, a resistor R4, a resistor R5, a diode D2, a triode Q3 and a triode Q4. According to the utility model, the input signal INPUT1 is input from the emitter of the triode Q2 instead of the base, so that on one hand, the circuit is a common-base amplification circuit, the switching characteristic is better, the response speed is high, on the other hand, the transition time of the triode Q2 in an amplification region when the triode Q2 is turned on and off can be effectively shortened, and the power consumption and heat emission of the triode Q2 are reduced; and the double-purpose effect is achieved.

The invention discloses a downward arch bridge type VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor) device. The downward arch bridge type VDMOSFET device is provided with symmetrical step-shaped grooves which are formed by etching a semiconductor layer of the downward arch bridge type VDMOSFET device; the inner wall and two sides of the stepped groove are covered with a layer of first gate dielectric; a second gate medium is also arranged on the first gate medium in the step-shaped groove; the first gate dielectric and the second gate dielectric jointly form a thickened gate dielectric layer of the downward arch bridge type VDMOSFET device; the semiconductor layer is provided with a diversion region and a drift region, and the diversion region extends downwards from the surface of the stepped groove to the drift region. Under the condition that the minimum line width of the device is not reduced, the cell size of the arch bridge type VDMOSFET is reduced, and meanwhile the good dynamic characteristic is obtained by reducing the gate-drain capacitance; and the deeper P well and the thicker gate dielectric layer ensure the reliability of the device.

The application discloses a SiC MOSFET device with improved diode reverse recovery characteristics and a preparation method thereof, and relates to the technical field of semiconductors.The device comprises, from bottom to top, a drain metal layer, an N-type substrate, a first N-type drift layer, a second N-type drift layer, a P-body region, a P+ contact region, an ohmic contact alloy layer and a source metal layer; a P++ layer extending downward is arranged in the middle of the top surface of the second N-type drift layer; a groove region extending into the P++ layer (4) is arranged on the top surface of the P+ contact region; a gate oxide layer is arranged in the groove region; a filled polysilicon gate is arranged in the gate oxide layer; N+ regions extending downward from the top surface of the P+ contact region into the P-body region are arranged on both sides of the groove region; an isolation medium layer is deposited on the P+ contact region, and the isolation medium layer completely covers the top end surfaces of the polysilicon gate and the gate oxide layer.The application can reduce the deep diffusion of carriers, make the recombination of the carriers better distributed in the surface region of the PN junction, and guarantee the long-term reliability of the device.

The invention discloses a segmented polycrystalline silicon deep groove silicon carbide MOSFET, and belongs to the technical field of semiconductor power devices. According to the device, a P + polycrystalline silicon section connected with a source electrode, a lightly doped Npolycrystalline silicon section and an N + polycrystalline silicon section connected with a grid electrode are sequentially arranged in a deep groove in the depth direction, and the P + polycrystalline silicon section, the lightly doped Npolycrystalline silicon section and the N + polycrystalline silicon section jointly form a polycrystalline silicon diode structure similar to a PIN. The P + polycrystalline silicon section at the bottom of the groove is used for shielding an electric field, the gate-drain coupling capacitance (Cgd) is effectively reduced, and the switching characteristic of the device is improved; meanwhile, by utilizing the characteristic that the reverse leakage current of the PIN structure is obviously increased under the short-circuit temperature rise, the self-adaptive reduction of the gate-source voltage (Vgs) is realized through gate loop resistance voltage division, so that the short-circuit current is inhibited. While voltage resistance and conduction performance of the device are ensured, short-circuit endurance capability and safe turn-off reliability of the device are remarkably improved.

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device including an IGBT having improved switching characteristics is provided. A trench gate electrode and a trench emitter electrode are formed through a gate insulating film inside a trench formed inside a semiconductor substrate of an active cell. An n-type hole isolation region is formed inside the semiconductor substrate between the trenches. A p-type base region is formed inside the hole isolation region. An n-type emitter region is formed inside the base region. A p-type floating region is formed inside the semiconductor substrate of the passive cell. A depth of the floating region is shallower than each depth of the trench and deeper than a depth of the base region.

The invention provides a junction-free transistor with a planar core-shell structure, which comprises a substrate, a core layer, a shell layer, a source-drain region, a grid electrode and a first side wall, the substrate, the core layer, the shell layer and the source-drain region are sequentially stacked along the stacking direction, the grid electrode and the first side wall are arranged on the same layer, the first side wall is arranged between the grid electrode and the source-drain region, and the first dielectric constant of the first side wall is greater than 7.5. In the stacking direction, the projection area of the shell layer in the plane where the substrate is located at least covers the projection areas of the grid electrode and the side wall in the plane where the substrate is located. By arranging the first side wall with a relatively high dielectric constant, the trend that the threshold voltage drops along with the shortening of the channel length can be slowed down, the roll-off of the threshold voltage can be inhibited, and the first side wall with the relatively high dielectric constant can also enhance the control capability of the grid electrode on the channel, improve the switching characteristic and inhibit the subthreshold swing degradation. And the modulation of the leakage voltage on the threshold voltage can be effectively suppressed, the leakage induced barrier lowering effect is weakened, and the suppression effect on the short channel effect is realized.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

The invention provides a thin film transistor, a preparation method thereof and a display panel. The thin film transistor comprises a substrate, a grid electrode, an insulating layer, an active layer, a protective layer, a source electrode and a drain electrode, the insulating layer covers the grid electrode; the active layer is arranged on one side of the insulating layer away from the substrate; the protective layer is arranged on one side, away from the substrate, of the active layer, and the material of the protective layer comprises Al2O3 and SiOxNy; the source electrode and the drain electrode are arranged on the side, away from the substrate, of the insulating layer and further cover part of the active layer and part of the protective layer. According to the thin film transistor, the protection layer containing Al2O3 and SiOxNy is arranged on the active layer, so that the influence of external environmental factors on the active layer can be effectively blocked, defects such as oxygen vacancies in the active layer are reduced, the active layer is effectively protected, the electrical performance of the thin film transistor is improved, threshold voltage drift is effectively inhibited, and the performance of the thin film transistor is improved. The stability and reliability of the display panel are remarkably improved, the quality of a display picture is improved, and the service life of the display panel is prolonged.

The present invention relates to the technical field of power semiconductor modules, and proposes a low-inductance packaging structure of a power semiconductor module, comprising a substrate and a power semiconductor module unit arranged on the substrate, the power semiconductor module unit is used to form a dual-switch circuit structure capable of reducing inductance, the power semiconductor module unit comprises a plurality of lining plates arranged at intervals on the substrate, adjacent lining plates are connected by a first bonding wire, two connected lining plates are connected with a power terminal group extending out of an outer tube shell, the power terminal group comprises two sub-power terminals which are partially overlapped but not in contact with each other, and are used to generate electromagnetic coupling when the two sub-power terminals conduct currents in different directions to reduce inductance; a low-inductance packaging method of a power semiconductor module is also proposed, which is used to manufacture the low-inductance packaging structure of a power semiconductor module proposed by the present invention. The present invention has the advantages of high reliability, high power density and low inductance.

The invention provides a method for reducing miller capacitance of a super junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises the following steps of: providing a substrate, and forming an epitaxial layer above the substrate; defining a forming region of a super junction structure according to photoetching, and etching the epitaxial layer to form a groove; filling a P-type material in the groove to form a P-type column; forming a JFET (Junction Field Effect Transistor) region, gate polysilicon and a thick oxygen or split gate structure between the JFET region and the gate polysilicon; and performing ion implantation and propulsion on the epitaxial layer to form a well region and a source region. According to the invention, the thick oxygen or split gate structure is embedded between the lower part of the gate polysilicon and the upper part of the JFET region, so that the gate-drain capacitance of the super junction device is reduced, and the switching characteristic is improved.

This invention discloses an integrated device with a gate array structure and its fabrication method, relating to the field of semiconductor device technology. The device includes: a substrate; a buffer layer located on one side of the substrate; a channel layer located on the side of the buffer layer facing away from the substrate; a barrier layer located on the side of the channel layer facing away from the substrate; a passivation layer located on the side of the barrier layer facing away from the substrate; a first trench penetrating the passivation layer and the barrier layer, and at least a portion of the channel layer, in a direction perpendicular to the substrate; a second trench penetrating the passivation layer and the barrier layer, in a direction perpendicular to the substrate; the second trench being located between the first trenches; a first gate serving as a radio frequency gate, comprising a first branch and a second branch, the first branch being located within the first trench of the channel layer, and the second branch being located within the second trench, the first branch and the second branch forming an array structure; a second gate being a DC gate; the second gate and the first gate being arranged at intervals along a second direction. This application can effectively ensure high signal linearity of the integrated device.

The utility model discloses a high-performance groove type IGBT device structure, which relates to the field of semiconductor devices and comprises a substrate of a first conductive type and an active region prepared in a central region of the substrate. A second conductive type base region corresponding to the front surface of the substrate and traversing the active region, and a first conductive type carrier storage layer traversing the second conductive type base region are arranged in the first conductive type substrate; the first conduction type carrier storage layer divides the second conduction type base region into a second conduction type first base region and a second conduction type second base region, and the second conduction type first base region is located above the second conduction type second base region; the first conductive type carrier storage layer is isolated from the first conductive type substrate through the second conductive type second base region. According to the IGBT device, the influence of the first conductive type charge storage layer on the breakdown voltage of the device is eliminated, and the IGBT device has relatively small saturation voltage drop and good switching characteristics.

The invention provides a motor controller, a power system and a vehicle, and relates to the technical field of motors, the motor controller comprises a direct current bus capacitor unit, the direct current bus capacitor unit comprises a first capacitor and a second capacitor which are connected in series, the first capacitor and the second capacitor are adjacent, and at least parts of the first capacitor and the second capacitor are oppositely arranged; the first connecting bar assembly is used for connecting the first capacitor and the second capacitor in series; and the power unit is electrically connected with the first connecting bar assembly. According to the motor controller, the internal stray inductance of the motor controller can be reduced, the working efficiency of the system is improved, and the model selection cost of the bus capacitor and the power module is reduced.

The present invention provides a p-type stannous oxide film, the p-type stannous oxide film comprises 19-26at% of tin oxide, 50-60at% of stannous oxide and 20-25at% of tin; and the p-type stannous oxide film is also doped with 2-10at% of tantalum. The present invention also provides a thin film transistor, the active layer of which is the p-type stannous oxide film as claimed in claim 1. The present invention also provides a method for preparing the thin film transistor, comprising the following steps: using a P-type Si substrate as a gate, thermally oxidizing the substrate, so that a SiO2 film as a gate dielectric layer grows on the surface of the P-type Si substrate; magnetron sputtering the surface of the SiO2 film so that the stannous oxide film as an active layer is deposited on the surface of the SiO2 film; annealing the stannous oxide film; thermally evaporating the annealed P-type Si substrate so that a gold film as a source and drain electrode is deposited on the surface of the stannous oxide film.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

The utility model relates to the technical field of semiconductors, in particular to a high-voltage metal oxide semiconductor (MOS) diode, which comprises a packaging body, an MOS chip is arranged inside the packaging body, three pins are connected below the packaging body, the three pins are respectively connected with the MOS chip through a first aluminum wire and two second aluminum wires, and the first aluminum wire and the second aluminum wire are respectively connected with the MOS chip. And a source electrode, a grid electrode and a drain electrode are sequentially formed. A plurality of thimbles are arranged on an MOS chip, and a multi-thimble structure is used for carrying out die bonding on the MOS diode, so that the effective width of the MOS chip is increased, the resistance of the MOS diode in a conducting state can be reduced, the conducting characteristic of a device is improved, meanwhile, the multi-thimble structure is adopted, the charge density on the MOS chip can be reduced, the charge voltage drop can be reduced, and the reliability of the device is improved. And the switching speed and the loss characteristic of the device are improved, so that the stress on the MOS chip is dispersed, and the risk of crystal cracking is further reduced.

The present invention relates to the field of semiconductor technology, and in particular to an integrated heterojunction trench gate field effect transistor, comprising an n-type silicon substrate, a first conductive type field stop layer and a first conductive type semiconductor drift region stacked in sequence from bottom to top, and a conductive module comprising a second conductive type electric field shielding region a, a second conductive type semiconductor deep well region, a second conductive type electric field shielding region b and a portion of a second type of conductive material arranged in sequence from outside to inside. The present application is based on the structure of a traditional trench gate MOSFET device, and a hexagonal trench is set to increase the channel area of ​​the device, thereby increasing the current density and reducing the on-resistance. At the same time, the setting of the "gap" type structure and the P-type shielding layer delay the electric field strength of the gate, improve the reliability of the device, set an integrated heterojunction diode, improve the body diode, significantly reduce the reverse recovery charge and reverse turn-on voltage of the device, improve the switching characteristics, and thus reduce the total switching loss.

The application discloses a high-voltage MOS device, and relates to the technical field of semiconductors, comprising a substrate layer, a first epitaxial layer is stacked on the top of the substrate layer, a second epitaxial layer is stacked on the top of the first epitaxial layer, a gate metal is arranged on the second epitaxial layer, the gate metal is wrapped with a contact metal layer outside, the contact metal layer comprises a contact section in contact with the second epitaxial layer, a source metal is arranged on the top of the contact section, and a drain metal is arranged on the bottom of the substrate layer; wherein a first insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the left side, a second insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the right side, and a gap section is formed between the first insulating silicon section and the second insulating silicon section; a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer and opposite to the gap section; and a testing method of the high-voltage MOS device is also disclosed. The application has the advantages of safety and stability, high reliability and strong anti-single-particle radiation capacity.

The utility model provides a full-bridge DC-DC conversion pulse width modulation signal driving circuit. The full-bridge DC-DC conversion pulse width modulation signal driving circuit comprises an input shaping driving circuit, an oscillation isolation circuit and an output driving circuit, the input shaping drive circuit is electrically connected with the oscillation isolation circuit and is used for carrying out filtering shaping on an input PWM control signal; the oscillation isolation circuit is electrically connected with the input shaping drive circuit and the output drive circuit and is used for isolating the PWM control signal; and the output driving circuit is electrically connected with the oscillation isolation circuit and is used for reducing the power loss of the main power MOS tube and improving the working efficiency of the full-bridge DC-DC conversion circuit. The input shaping drive circuit carries out filtering shaping on PWM control signals to improve the drive capability, the oscillation isolation circuit realizes undistorted synchronous isolation transmission of four paths of PWM signals to ensure that the drive circuit is safe and reliable, the output drive circuit is optimally designed to reduce the switching loss of a power MOS tube, and the output drive circuit is optimized. Therefore, the control signal quality, the isolation synchronism and the working efficiency of the full-bridge DC-DC conversion power circuit are improved, and the performance and the reliability of the whole system are effectively improved.

The invention provides a silicon carbide floating junction structure with an N-type thin layer and improved switching characteristics, and relates to the technical field of semiconductor power devices. Comprising an N-type substrate; the N-type drift region is formed on the N-type substrate; the plurality of P-type floating junctions are formed in the N-type drift region and are arranged at intervals; the N-type thin layers are formed between the P-type floating junctions and on the two sides of the P-type floating junctions, so that the N-type thin layers are in contact connection with the P-type floating junctions; the plurality of P-type doped regions are formed in the N-type drift region and are arranged at intervals, and the plurality of P-type doped regions and the plurality of P-type floating junctions are arranged up and down; the ohmic contact metal is formed on the lower surface of the N-type substrate; and the Schottky contact metal is formed on the N-type drift region and the plurality of P-type doped regions. More N-type carriers are introduced into the plurality of N-type thin layers, the barrier broadening effect at intervals of floating junctions during reverse bias is improved, disappearance of the barrier is accelerated during positive bias, overcharge voltage is not generated, and the starting speed is high when starting is carried out after turn-off.