7results about How to "Improve switching characteristics" patented technology

The application discloses a SiC MOSFET device with improved diode reverse recovery characteristics and a preparation method thereof, and relates to the technical field of semiconductors.The device comprises, from bottom to top, a drain metal layer, an N-type substrate, a first N-type drift layer, a second N-type drift layer, a P-body region, a P+ contact region, an ohmic contact alloy layer and a source metal layer; a P++ layer extending downward is arranged in the middle of the top surface of the second N-type drift layer; a groove region extending into the P++ layer (4) is arranged on the top surface of the P+ contact region; a gate oxide layer is arranged in the groove region; a filled polysilicon gate is arranged in the gate oxide layer; N+ regions extending downward from the top surface of the P+ contact region into the P-body region are arranged on both sides of the groove region; an isolation medium layer is deposited on the P+ contact region, and the isolation medium layer completely covers the top end surfaces of the polysilicon gate and the gate oxide layer.The application can reduce the deep diffusion of carriers, make the recombination of the carriers better distributed in the surface region of the PN junction, and guarantee the long-term reliability of the device.

The invention discloses a segmented polycrystalline silicon deep groove silicon carbide MOSFET, and belongs to the technical field of semiconductor power devices. According to the device, a P + polycrystalline silicon section connected with a source electrode, a lightly doped Npolycrystalline silicon section and an N + polycrystalline silicon section connected with a grid electrode are sequentially arranged in a deep groove in the depth direction, and the P + polycrystalline silicon section, the lightly doped Npolycrystalline silicon section and the N + polycrystalline silicon section jointly form a polycrystalline silicon diode structure similar to a PIN. The P + polycrystalline silicon section at the bottom of the groove is used for shielding an electric field, the gate-drain coupling capacitance (Cgd) is effectively reduced, and the switching characteristic of the device is improved; meanwhile, by utilizing the characteristic that the reverse leakage current of the PIN structure is obviously increased under the short-circuit temperature rise, the self-adaptive reduction of the gate-source voltage (Vgs) is realized through gate loop resistance voltage division, so that the short-circuit current is inhibited. While voltage resistance and conduction performance of the device are ensured, short-circuit endurance capability and safe turn-off reliability of the device are remarkably improved.

The invention provides a junction-free transistor with a planar core-shell structure, which comprises a substrate, a core layer, a shell layer, a source-drain region, a grid electrode and a first side wall, the substrate, the core layer, the shell layer and the source-drain region are sequentially stacked along the stacking direction, the grid electrode and the first side wall are arranged on the same layer, the first side wall is arranged between the grid electrode and the source-drain region, and the first dielectric constant of the first side wall is greater than 7.5. In the stacking direction, the projection area of the shell layer in the plane where the substrate is located at least covers the projection areas of the grid electrode and the side wall in the plane where the substrate is located. By arranging the first side wall with a relatively high dielectric constant, the trend that the threshold voltage drops along with the shortening of the channel length can be slowed down, the roll-off of the threshold voltage can be inhibited, and the first side wall with the relatively high dielectric constant can also enhance the control capability of the grid electrode on the channel, improve the switching characteristic and inhibit the subthreshold swing degradation. And the modulation of the leakage voltage on the threshold voltage can be effectively suppressed, the leakage induced barrier lowering effect is weakened, and the suppression effect on the short channel effect is realized.

The invention provides a thin film transistor, a preparation method thereof and a display panel. The thin film transistor comprises a substrate, a grid electrode, an insulating layer, an active layer, a protective layer, a source electrode and a drain electrode, the insulating layer covers the grid electrode; the active layer is arranged on one side of the insulating layer away from the substrate; the protective layer is arranged on one side, away from the substrate, of the active layer, and the material of the protective layer comprises Al2O3 and SiOxNy; the source electrode and the drain electrode are arranged on the side, away from the substrate, of the insulating layer and further cover part of the active layer and part of the protective layer. According to the thin film transistor, the protection layer containing Al2O3 and SiOxNy is arranged on the active layer, so that the influence of external environmental factors on the active layer can be effectively blocked, defects such as oxygen vacancies in the active layer are reduced, the active layer is effectively protected, the electrical performance of the thin film transistor is improved, threshold voltage drift is effectively inhibited, and the performance of the thin film transistor is improved. The stability and reliability of the display panel are remarkably improved, the quality of a display picture is improved, and the service life of the display panel is prolonged.

This invention discloses an integrated device with a gate array structure and its fabrication method, relating to the field of semiconductor device technology. The device includes: a substrate; a buffer layer located on one side of the substrate; a channel layer located on the side of the buffer layer facing away from the substrate; a barrier layer located on the side of the channel layer facing away from the substrate; a passivation layer located on the side of the barrier layer facing away from the substrate; a first trench penetrating the passivation layer and the barrier layer, and at least a portion of the channel layer, in a direction perpendicular to the substrate; a second trench penetrating the passivation layer and the barrier layer, in a direction perpendicular to the substrate; the second trench being located between the first trenches; a first gate serving as a radio frequency gate, comprising a first branch and a second branch, the first branch being located within the first trench of the channel layer, and the second branch being located within the second trench, the first branch and the second branch forming an array structure; a second gate being a DC gate; the second gate and the first gate being arranged at intervals along a second direction. This application can effectively ensure high signal linearity of the integrated device.

The invention provides a motor controller, a power system and a vehicle, and relates to the technical field of motors, the motor controller comprises a direct current bus capacitor unit, the direct current bus capacitor unit comprises a first capacitor and a second capacitor which are connected in series, the first capacitor and the second capacitor are adjacent, and at least parts of the first capacitor and the second capacitor are oppositely arranged; the first connecting bar assembly is used for connecting the first capacitor and the second capacitor in series; and the power unit is electrically connected with the first connecting bar assembly. According to the motor controller, the internal stray inductance of the motor controller can be reduced, the working efficiency of the system is improved, and the model selection cost of the bus capacitor and the power module is reduced.

The application discloses a high-voltage MOS device, and relates to the technical field of semiconductors, comprising a substrate layer, a first epitaxial layer is stacked on the top of the substrate layer, a second epitaxial layer is stacked on the top of the first epitaxial layer, a gate metal is arranged on the second epitaxial layer, the gate metal is wrapped with a contact metal layer outside, the contact metal layer comprises a contact section in contact with the second epitaxial layer, a source metal is arranged on the top of the contact section, and a drain metal is arranged on the bottom of the substrate layer; wherein a first insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the left side, a second insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the right side, and a gap section is formed between the first insulating silicon section and the second insulating silicon section; a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer and opposite to the gap section; and a testing method of the high-voltage MOS device is also disclosed. The application has the advantages of safety and stability, high reliability and strong anti-single-particle radiation capacity.