28 results about "Substrate bias voltage" patented technology

The invention relates to the technical field of film preparation, in particular to a preparation process of a nitrogen-doped carbon film for modifying the surface of a substrate, which comprises the following preparation steps: S1, pretreating the substrate; s2, composite etching treatment; s3, dynamic surface modification; s4, performing magnetron co-sputtering deposition; and S5, gradient annealing treatment. By introducing the electroactive monomer and adjusting the substrate bias voltage in the deposition process and the annealing temperature after deposition, the chemical bond state of N is controlled, the ORR catalytic activity is optimized, it is proved that the ORR catalytic activity of the nitrogen-doped carbon film directly depends on the content of pyridine N in the film, and it is indicated that pyridine N is the effective catalytic active site of ORR.

According to one embodiment, a semiconductor memory device includes an input and output pad group, a memory cell array including a plurality of memory cells, and an input and output circuit provided between the input and output pad group and the memory cell array. The input and output circuit includes a plurality of transistors, and a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors.

The invention discloses a clock voltage doubling circuit, a reference circuit and a chip, the clock voltage doubling circuit comprises a target clock generation module, the target clock generation module comprises a first target clock generation unit, a second target clock generation unit and a substrate effect elimination unit, a substrate effect elimination unit generates a substrate bias voltage greater than a power supply voltage according to the power supply voltage, a first intermediate clock signal and a second intermediate clock signal; compared with P-channel transistors in the first target clock generation unit and the second target clock generation unit, the P-channel transistors in the first target clock generation unit and the second target clock generation unit adopt power supply voltage as substrate voltage and have higher conduction impedance, and the bulk effect of the P-channel transistors can be reduced, so that the conduction impedance is reduced, and the overall power consumption is further reduced.

This application provides a buffer and chip. The buffer includes a first conversion circuit, a second conversion circuit, and a common-mode feedback circuit. The first conversion circuit outputs a first output signal based on a first input signal, a first bias voltage, and a first substrate bias voltage of a first main input transistor. The first substrate bias voltage includes an initial and an adjusted first substrate bias voltage. The second conversion circuit outputs a second output signal based on a second input signal, the first bias voltage, and a second substrate bias voltage of a second main input transistor. The second substrate bias voltage includes an initial and an adjusted second substrate bias voltage. The common-mode feedback circuit generates a common-mode signal based on the first and second output signals. Based on the common-mode signal and a target voltage value, it generates and adjusts the first and second substrate bias voltages based on the feedback signal. Because the common-mode feedback circuit adjusts the substrate voltage of the main input transistor, it maintains the stability of the common-mode signal, thereby improving the linearity and stability of the buffer.

The invention discloses a wide-swing output stage circuit. The wide-swing output stage circuit comprises a substrate bias control unit and an output stage circuit, wherein the substrate bias control unit is used for generating substrate bias voltages VBP and VBN according to output swing requirements and outputting the substrate bias voltages VBP and VBN to the output stage unit, and the output stage unit generates output signals meeting the output swing requirements by accessing the substrate bias voltages. According to the scheme, the swing increasing circuit is simple in structure and convenient to control, high-voltage devices and expensive complex processes are not needed, high-swing output can be achieved by adopting a conventional common commercial CMOS process tape-out, under the condition that a power supply is not increased, the output swing of a processing signal is increased by adjusting the substrate voltage of the MOS transistor output by the operational amplifier, and therefore the signal processing efficiency is improved. The dynamic range of an analog integrated circuit designed by applying the operational amplifier of the type can be effectively improved, and the operational amplifier is very suitable for the design of a low-power-supply-voltage analog integrated circuit with a smaller deep submicron size.

In a film formation apparatus and a film formation method using magnetron sputtering, high reproducibility is achieved even when a reactive film is formed by simultaneously introducing a plurality of types of reactive gases into a vacuum chamber. [Solution] In a magnetron sputtering apparatus (10) according to the present invention, the flow rate Qd of an inert gas introduced into a vacuum chamber (12) is kept constant, and the angle θ of a conductance valve (22) is kept constant, i.e., the effective pumping speed at an exhaust port (14) of the vacuum chamber (12) is kept constant. Additionally, the sputtering power Es, the arc discharge power Ed, and the substrate bias voltage Vb are kept constant. Furthermore, a gas flow rate ratio Rq, which is the ratio between the flow rates Qr1 and Qr2 of the reactive gases introduced into the vacuum chamber (12), is kept constant, and a total gas flow rate Qa, which is the sum of the flow rates Qr1 and Qr2 of the reactive gases, is controlled so that the pressure P inside the vacuum chamber (12) is kept constant.

The invention provides a ceramic coating with excellent wear resistance and a preparation method and application thereof, and relates to the technical field of ceramic coating preparation, the ceramic coating is composed of Ti, Mo, B and N. The content range of the Mo element is 16.1-36.8 at.%. The invention also provides a preparation method of the ceramic coating. The preparation method comprises the following steps: cleaning the substrate; argon is introduced, the power of the Ti target is adjusted, and first deposition is carried out; and argon and nitrogen are introduced, the TiB2 target, the Ti target and the Mo target are opened, secondary deposition is carried out on the substrate coated with the Ti transition layer, the flow of the nitrogen is 5.2-7.2 sccm, the bias voltage of the substrate is-140-80 V in the secondary deposition process, and the high-wear-resistance ceramic coating is obtained. The high-wear-resistance ceramic coating disclosed by the invention has relatively good wear resistance.

This invention discloses a highly conductive and corrosion-resistant coating for titanium bipolar plates used in PEMWE hydrogen production, its preparation method, and its application. The preparation method includes the following steps: Step 1: A Ti seed layer is deposited on a substrate using magnetron sputtering, with a Ti target power of 100~130 W and a substrate bias voltage of -100~-250 V; Step 2: A TiMo alloy transition layer is deposited on the surface of the Ti seed layer using magnetron sputtering; Step 3: A TiMoC composite layer is deposited on the surface of the TiMo alloy transition layer using magnetron sputtering. This invention modifies titanium bipolar plates through a three-layer coating system formed by Ti / TiMo / TiMoC. The Ti seed layer improves the adhesion between the coating and the substrate, the TiMo alloy transition layer enhances corrosion resistance, and the TiMoC composite layer improves conductivity while ensuring corrosion resistance. The resulting coating exhibits excellent comprehensive performance in the PEMWE hydrogen production environment.

The invention discloses a coating method of multi-arc ion plating equipment and an arc source device of the multi-arc ion plating equipment, and relates to the technical field of coating, the multi-arc ion plating equipment comprises a vacuum cavity, and a rotatable sample table and vertically arranged arc source units are arranged in the vacuum cavity; the arc source unit comprises a cathode target material, an arc striking assembly and a dynamic magnetic field adjusting module. The cathode target materials are vertically arranged, and the included angle between the centers of the adjacent target materials is 30-45 degrees; the dynamic magnetic field adjusting module comprises a permanent magnet and an electromagnetic coil set, the magnetic field intensity (0-500 Gs) and the direction are adjusted in real time through a PLC, and the movement speed (10-50 cm / s) of an arc light spot is controlled. According to the invention, a coordinated control system integrates linkage adjustment functions of arc current (50-200 A), gas flow (Ar: 50-200 sccm, N2: 100-1000 sccm) and substrate bias voltage (-50--500 V), compared with annular staggered arrangement equipment, the occupied space is smaller, 3-4 groups of arc sources can be arranged, and the coating efficiency is improved.

The invention provides a semiconductor memory device capable of suppressing power consumption. A semiconductor memory device (2) includes an input / output pad group (32), a memory cell array (21) including a plurality of memory cells, and an input / output circuit (22) provided between the input / output pad group (32) and the memory cell array (21). An input / output circuit (22) is provided with: a plurality of transistors (QH1, QL1); and substrate bias voltage supply circuits (40, 41) capable of switching between a first voltage having the same value as the power supply voltage of the input / output circuit and a second voltage having a different value from the first voltage to supply as the substrate bias voltages of the plurality of transistors (QH1, QL1).

To provide a semiconductor memory device that can suppress power consumption. [Solution] The semiconductor memory device 2 comprises an input / output pad group 32, a memory cell array 21 including a plurality of memory cells, and an input / output circuit 22 provided between the input / output pad group 32 and the memory cell array 21. The input / output circuit 22 comprises a plurality of transistors QH1, QL1, and substrate bias voltage supply circuits 40, 41 that can switch between supplying a first voltage with the same value as the power supply voltage of the input / output circuit and a second voltage with a different value from the first voltage as the substrate bias voltage of the plurality of transistors QH1, QL1.

The invention discloses a low-ripple charge pump circuit, and the circuit comprises a non-overlapping clock circuit which is used for generating a first clock signal and a second clock signal which are not overlapped according to an external clock signal; and the charge pump main body circuit is used for boosting the input voltage according to the first clock signal and the second clock signal to form charge pump output voltage and dynamic substrate bias voltage. According to the OTP memory circuit, the loss of reverse leakage current can be effectively reduced by adopting the non-overlapping clock signals, the reverse leakage current caused by conduction of a path between input and output due to simultaneous conduction of the switching tubes of the charge pump is avoided, and the OTP memory circuit can meet the requirements of high stability and low loss of the OTP memory circuit.

This invention discloses a high-speed analog multiplier circuit, belonging to the field of integrated circuit signal processing. It improves high-frequency performance by dynamically adjusting the tail current through a frequency detection network. This network amplifies the differential signal V2 via a differential-to-single-ended converter, then attenuates high-frequency components through a low-pass RC filter. The comparator output controls the substrate bias voltage of the tail current source. As the frequency of V2 increases, the substrate bias voltage increases, utilizing the NMOS substrate bias effect to lower the threshold voltage, thereby increasing the tail current and compensating for high-frequency gain attenuation. Two alternative solutions are provided: a parallel transistor and a self-biased tail current source. This circuit has a simple structure, significantly extends the multiplier bandwidth, and is suitable for high-speed communication and signal processing systems.

The invention discloses a strobe gate, a reference circuit and a chip, the strobe gate comprises a first transmission tube and a second transmission tube, the influence of the bulk effect can be reduced, the conduction impedance and the leakage current of the second transmission tube can be reduced by connecting a power supply voltage greater than or equal to N times to the substrate of the second transmission tube as a substrate bias voltage, and the reliability of the strobe gate can be improved. Therefore, the conduction impedance and the leakage current of the gating gate are reduced, and the overall power consumption is reduced.

An interface circuit, a method for controlling the interface circuit, a chip, and a terminal device are provided. The interface circuit includes a first PMOS transistor, an input signal control circuit, a bias circuit, a signal input end, and an input / output end. The bias circuit includes a substrate bias voltage generation end and a bias voltage generation end. The bias circuit is coupled to a high-level power supply end, the input / output end, and a ground end. The input signal control circuit is connected to the signal input end, the bias voltage generation end, and a gate of the first PMOS transistor; a first electrode of the first PMOS transistor is connected to the high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input / output end.

A threshold-adjustable inverter circuit with self-adaptive substrate bias comprises an operational amplifier, a main inverter, a replica inverter and a substrate bias generation circuit, the main inverter, the replica inverter and the substrate bias generation circuit are connected with the operational amplifier, and the positive input end of the operational amplifier is connected with the replica inverter with input and output short circuit. The output end of the operational amplifier is connected with the substrate bias generation circuit through the bias resistor and further connected to the substrate bias voltage ends of the main phase inverter and the replica phase inverter, and the input end and the output end of the main phase inverter serve as the input end and the output end of the adjustable threshold phase inverter circuit; the operational amplifier compares threshold voltage output by the replica inverter with external set voltage and outputs a control signal to the substrate bias generation circuit, substrate bias voltage of the main inverter and the replica inverter is generated, the replica inverter threshold value is locked to the external set voltage through a negative feedback mechanism, the bias voltage is applied to the main inverter, and the main inverter and the replica inverter are connected. And self-adaptive adjustment of the threshold value is realized. Closed-loop negative feedback is formed by copying the phase inverter and the operational amplifier, real-time tracking and calibration of the threshold voltage are achieved, accurate control over the threshold voltage of the phase inverter is actively achieved by adjusting the substrate voltage, and the threshold value is kept stable under changes of the technology, the voltage and the temperature. The circuit is suitable for a low-power-consumption and high-stability digital circuit and analog mixed signal system, can replace the traditional fixed threshold design, and improves the robustness of the system.

A method and apparatus for biasing regions of a substrate in a plasma assisted processing chamber is provided. Biasing the substrate (or regions of the substrate) increases the potential difference between the substrate and a plasma formed in the processing chamber, thereby accelerating ions from the plasma toward the active surface of the substrate region. The plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that facilitates managing uniformity of processing results across the substrate.

The invention discloses a high-speed analog multiplier circuit, belongs to the field of integrated circuit signal processing, and improves high-frequency performance by dynamically adjusting tail current through a frequency detection network. According to the network, after an input signal V is subjected to differential-to-single-ended amplification, a high-frequency component is attenuated through low-pass RC filtering, and a comparator outputs a control tail current source substrate bias voltage. When the Vfrequency is increased, the substrate bias voltage is increased, and the threshold voltage is reduced by using the NMOS substrate bias effect, so that the tail current is increased, and the high-frequency gain attenuation is compensated. Meanwhile, two alternative schemes of a parallel triode and a self-bias tail current source are provided. The circuit is simple in structure, remarkably expands the bandwidth of the multiplier, and is suitable for high-speed communication and signal processing systems.

The application discloses a pixel circuit and a control method thereof, an electronic device, a storage medium and a program product, which is suitable for Micro OLED, which can compensate for the difference in transistor threshold voltage characteristics between different pixels. The pixel circuit includes: a light-emitting circuit, a driving circuit, a compensation circuit and a switching circuit. The light-emitting circuit in the pixel circuit is in a light-emitting state before at least the pixel circuit is controlled to be in a discharge stage, and in the discharge stage, the substrate of the driving transistor can be discharged through the compensation circuit to compensate the substrate bias voltage of the driving transistor.

The plasma processing apparatus includes: a plasma processing chamber; a variable impedance element; the substrate supporting part is arranged in the plasma processing chamber and comprises a conductive base; an electrostatic chuck; an edge ring; a substrate bias electrode; a ring bias electrode; an additional electrode electrically connected to a ground potential via the variable impedance element; and at least one connector electrically connected to the edge ring and the conductive abutment; and at least one voltage pulse generation unit electrically connected to the substrate bias electrode and the ring bias electrode and configured to generate a pulsed voltage signal.

The invention discloses a preparation method of a high-performance coating based on HiPIMS multi-target high-speed deposition and a cutting tool thereof. The preparation method comprises the steps of substrate pretreatment, substrate surface cleaning, multi-target co-sputtering deposition and the like. In the step of multi-target co-sputtering deposition, a plurality of targets of the same type are started, a coating is deposited on the surface of a substrate in a mixed atmosphere of reaction gas and inert gas by adopting a high-power pulse magnetron sputtering technology under the action of substrate bias voltage, and in the deposition process, the coating is deposited on the surface of the substrate on the basis of a preset total pulse power. And the pulse power applied to each single target material is independently regulated and controlled according to a non-uniform power distribution model, so that the pulse power of each target material is distributed in a proportionally decreasing manner. According to the preparation method provided by the invention, the deposition rate can be effectively increased to meet industrial production requirements, and meanwhile, the coating and the cutting tool with the coating can be ensured to have relatively high use performance.

A plasma source (100) for surface treating one or more substrates (116), comprising: a vacuum chamber (108); a voltage source (128); a material feed source (130); a magnet arrangement (122a, 122b) having magnets (112, 112a), the magnets (112, 112a), preferably permanent magnets (112a), being oriented relative to one another in such a way that electron cyclotron resonance conditions are satisfied; an instrument (126) for generating and transmitting electromagnetic waves (120), where the instrument (126) comprises a generator (104) for generating electromagnetic waves (120), an antenna (102) and a conductor (106); and at least one or more substrate holding devices, such as a substrate tree structure, for holding the one or more substrates (116), in which a substrate bias that can be switched on and off can be applied to the one or more substrates (116) by means of a voltage source (128).

The invention discloses a method for realizing low-temperature preparation of an Nb3Sn thin film through high-power pulse magnetron sputtering and application of substrate bias voltage, and relates to a method for realizing low-temperature preparation of the Nb3Sn thin film. The invention aims to solve the problem that a pure-phase Nb3Sn film with excellent superconducting performance cannot be prepared at the temperature lower than 800 DEG C in the prior art. The method comprises the steps of 1, substrate preparation and pretreatment; 2, low-temperature heating and atmosphere control; 3, bias voltage assisted high-power pulse magnetron sputtering is carried out; and 4, in-situ cooling and sampling. The low-temperature preparation method is used for realizing low-temperature preparation of the Nb3Sn film through high-power pulse magnetron sputtering and application of the substrate bias voltage.

An electronic system device includes a power generation device that generates a power supply voltage, a substrate bias generation circuit connected to the power generation device, a memory circuit, a monitoring circuit, and a capacitor connected to the substrate bias generation circuit via a switch. The substrate bias generation circuit generates a substrate bias voltage from the power supply voltage, and supplies electric charge to the capacitor based on the substrate bias voltage when the switch is in an on state. The capacitor stores accumulated electric charge based on the substrate bias voltage when the switch is in an off state. The substrate bias generation circuit adds to the held electric charge based on the substrate bias voltage when the switch is in the on state, and declares a reverse bias voltage. The substrate bias generation circuit supplies the reverse bias voltage to the memory circuit.

Embodiments of the disclosure include a method for fabricating a semiconductor device, comprising: forming, within a physical vapor deposition (PVD) chamber, a first layer by use of a PVD process on a surface of substrate that comprises a plurality of features formed therein, wherein forming the first layer comprises biasing a target within the process chamber; and etching, within the PVD chamber, at least a portion of the first layer. The etching process comprises: applying a substrate bias to an electrode disposed within a substrate support near a substrate receiving surface, wherein applying the substrate bias comprises delivering a pulsed-voltage (PV) waveform to the electrode; and exposing the substrate to a plasma generated within the PVD chamber.

Provided is a technique capable of suppressing variation in the angle of incidence of ions at the edge portion of a substrate in plasma processing. A plasma processing apparatus includes: a chamber; a substrate support portion; an RF generator configured to generate an RF signal for generating plasma in the chamber; a substrate bias signal generator electrically connected to a substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse trains; and a ring bias signal generator electrically connected to a ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse trains, each of the plurality of second voltage pulse trains including a plurality of voltage pulses having gradually decreasing voltage levels.