31results about How to "Raise the threshold voltage" patented technology

The invention discloses a tunneling gate HEMT device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a transition layer, a buffer layer, a channel layer and a barrier layer, wherein the transition layer, the buffer layer, the channel layer and the barrier layer are sequentially located on the substrate layer; the p-GaN layer is located on the barrier layer; the isolation structure is located on the side wall of the HEMT device, and the isolation structure penetrates through the barrier layer and the channel layer and is located on the buffer layer; the passivation layer is located on the side wall of the p-GaN layer and on the barrier layer; the tunneling layer is positioned at the bottom and the side part of the grid opening area of the passivation layer; the grid electrode penetrates through the passivation layer and is positioned on the tunneling layer; and the source electrode and the drain electrode are respectively located at different sides of the p-GaN layer, and the source electrode and the drain electrode respectively penetrate through the passivation layer and are located on the barrier layer. Compared with the prior art, a layer of thin medium is deposited in the groove of the grid electrode to serve as the tunneling layer, so that the breakdown voltage of the grid electrode of the HEMT device is effectively improved.

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first region and a second region; the channel structure is suspended on the substrate, and the channel structure comprises one or more channel layers which are sequentially arranged at intervals from bottom to top; the gate structure stretches across the channel structure and surrounds the channel layer, and the gate structure comprises a work function layer surrounding the channel layer, a work function layer located between the channel layer and the substrate or located between the adjacent channel layers, a work function layer serving as a first work function layer, a work function layer located at the top of the topmost channel layer and a second work function layer; wherein the sum of the thickness of the first work function layer and the thickness of the second work function layer in the first area is larger than the sum of the thickness of the first work function layer and the thickness of the second work function layer in the second area. According to the embodiment of the invention, under the condition that the threshold voltage of the semiconductor device in the second region meets the requirement, the threshold voltage of the semiconductor device in the first region is improved, so that the semiconductor device can meet different functional requirements.

A first contact hole at the top of a source region is directly composed of a material layer of a front metal layer filled in an opening of the first contact hole, the front metal layer is made of AlSiCu, and the content of Si in the AlSiCu reaches a saturation value; the AiSiCu of the first contact hole directly forms ohmic contact with the source region and the semiconductor material of the first epitaxial layer of the second conductive type well, and by utilizing the characteristic that the content of Si in the AlSiCu reaches a saturation value, the sharp convex defect is prevented from being formed when the A1Cu directly contacts with the semiconductor material of the first epitaxial layer; by utilizing the characteristic that the resistivity of AlSiCu is greater than that of AlCu, the forward conduction voltage drop of the body diode is increased, and the reverse recovery characteristic of the device is improved. The reverse recovery charge can be reduced, and the reverse recovery characteristic of the device can be improved.

The invention discloses an enhanced MOSHEMT (Metal-Oxide-Semiconductor High Electron Mobility Transistor) device with an ultrahigh K dielectric wrapped groove gate, which structurally comprises a substrate, a buffer layer, a channel layer and a barrier layer in sequence, a source electrode and a drain electrode are respectively arranged on two sides of the barrier layer, a groove is arranged in the middle of the barrier layer close to the source electrode, a passivation layer is arranged in the area of the barrier layer except for the source electrode and the drain electrode, and a metal oxide semiconductor layer is arranged on the passivation layer. An ultrahigh K gate dielectric layer is arranged on the passivation layer, a groove gate is arranged above the ultrahigh K gate dielectric layer corresponding to the groove of the barrier layer, and an ultrahigh K dielectric layer is further arranged to cover the groove gate. The invention also discloses a preparation method. The enhanced HEMT device with high threshold voltage and high transconductance is realized by introducing a high-quality ultra-high K medium and utilizing polarization charges generated by the high-quality ultra-high K medium to assist depletion and accumulation of 2DEG under a gate; after the gate metal is deposited, the ultra-high K dielectric layer is secondarily covered to form a wrapped groove gate, a peak electric field can be effectively reduced by utilizing polarization charges, close to a drain end region, of the gate edge, and high breakdown voltage is achieved.

The invention discloses a p-channel gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The p-channel gallium nitride transistor comprises a substrate; the barrier layer and the p-type gallium nitride layer are located on one side of the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; the p-type gallium nitride layer comprises a first groove, and a first bulge and a second bulge which are positioned on two opposite sides of the first groove; the ratio range of the thickness L1 of the groove bottom of the first groove to the thickness L2 of the p-type gallium nitride layer at the first bulge and / or the second bulge is 1 / 14 < = L1 / L2 < = 3 / 14; a depletion layer located in the first groove; the depletion layer comprises a titanium metal layer and a titanium nitride layer which are laminated, and the titanium nitride layer is located between the titanium metal layer and the p-type gallium nitride layer; the source electrode and the drain electrode are located on the sides, away from the substrate, of the first protrusion and the second protrusion respectively; the grid electrode is located in the first groove and located on the side, away from the p-type gallium nitride layer, of the depletion layer. The stability and the electrical performance of the transistor are improved.

The utility model relates to the technical field of semiconductors, and provides a semiconductor device, which comprises a base layer, a buffer layer and a first gate metal layer, the buffer layer and the base layer are stacked; the first gate metal layer is arranged on one side of the buffer layer, and the first gate metal layer is a TiAlN first gate metal layer, a TaAlN first gate metal layer or a WalN first gate metal layer. According to the semiconductor device, the first gate metal layer is set to be the TiAlN first gate metal layer, the TaAlN first gate metal layer or the WalN first gate metal layer, the characteristic that the aluminum element is poor in work function is utilized, when the content of the aluminum element in the composition is reduced, the work function of the aluminum element can be adjusted, then the threshold voltage of the gate metal layer is increased, and the performance of the semiconductor device is improved. The regulation and control amplitude of the threshold voltage of the semiconductor device is increased, and the application requirement of driving the gate voltage in a wide range is met.

This invention discloses a method for manufacturing a trench gate semiconductor power device, comprising: forming a first hard mask layer on a first epitaxial layer; patterning and etching the first hard mask layer to open the formation region of the gate trench; etching the first epitaxial layer to form the gate trench; removing the first hard mask layer and then performing a first thermal oxidation process to form a first field oxide layer on the inner surface and outer surface of the gate trench; performing a first CVD growth process to form a second field oxide layer, and stacking the first and second field oxide layers to form a third field oxide layer; performing a first CMP process to remove the third field oxide layer outside the gate trench; forming a first polysilicon layer to completely fill the gate trench and extend it outside the gate trench; and performing a second CMP process to planarize the first polysilicon layer. This invention can simultaneously improve the structural consistency of the gate trench region and the plateau region, and can comprehensively improve the device performance and yield.

The invention discloses a writing method of a ferroelectric field effect transistor array, and belongs to the technical field of micro-nano electronics. According to the method, a self-compensation write-in method is provided for a multi-stage storage ferroelectric field effect transistor array of a 1T structure, a pulse sequence of a self-compensation waveform is adopted for write-in and corresponds to different storage states in multi-stage storage, positive pulse write-in is adopted when the pulse sequence is higher than an intermediate storage state, and negative pulse write-in is adopted when the pulse sequence is lower than the intermediate storage state. The method comprises the following steps of: writing a FeFET memory cell, performing read verification on a written state of the FeFET memory cell, starting an error correction program for correction when a write error is found so as to reach a target state, and starting a durability recovery program to recover the performance of the FeFET memory device if the error correction program fails; the method simultaneously solves the reliability problems of large fluctuation between devices and between cycles, limited durability and serious write-in crosstalk, has the advantages of simple process, low hardware overhead and the like, is compatible with the current advanced node CMOS technology, and is easy to implement.

A semiconductor structure and a method for forming the same, the semiconductor structure comprising: a substrate, the substrate comprising a first region; a first polarization layer located on the first region, the material of the first polarization layer being a semiconductor compound material having first polarization atoms; and a first gate structure located on the first polarization layer. Through the first polarization layer located on the first region, the material of the first polarization layer being a semiconductor compound material having first polarization atoms. Since the first polarization atoms in the first polarization layer directly form corresponding salt compounds with semiconductor materials, the first polarization layer can have a higher threshold voltage, and thus in a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, reducing the problem of the same threshold voltage of different gates, and effectively improving the performance of the semiconductor structure finally formed.

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.

The present invention discloses a normally closed heterojunction field effect transistor structure with high threshold voltage and high drain operating current and a preparation method thereof, which comprises, from bottom to top, a substrate, an AlN nucleation layer, an AlGaN buffer layer, a GaN channel layer with an NPN bipolar transistor structure, and an AlGaN barrier layer; a passivation layer is provided at both ends of the AlGaN barrier layer, and a GaN cap layer is provided on the AlGaN barrier layer; a gate electrode with a Schottky contact is led out from above the GaN cap layer, and a source electrode and a drain electrode with a Schottky contact are led out from both ends of the gate GaN channel layer. Compared with conventional devices, the present invention creatively introduces an NPN bipolar transistor structure in the GaN channel layer below the gate position, which can simultaneously increase the threshold voltage and drain operating current of the device.

The invention discloses a p-channel gallium nitride transistor and a preparation method thereof, and relates to the technical field of microelectronics. The p-channel gallium nitride transistor comprises a substrate; a barrier layer; the p-type gallium nitride layer comprises a first groove, a first bulge and a second bulge, the first bulge and the second bulge are positioned on two opposite sides of the first groove, and the thickness L1 of the bottom of the first groove is more than or equal to 10nm and less than or equal to 15nm; the zinc oxide layer is located in the first groove; the electrode structure comprises a source electrode, a grid electrode and a drain electrode, the source electrode is located on the side, away from the substrate, of the first protrusion, the drain electrode is located on the side, away from the substrate, of the second protrusion, and the grid electrode is located in the first groove and located on the side, away from the p-type gallium nitride layer, of the zinc oxide layer. According to the technical scheme of the invention, the zinc oxide layer is arranged between the grid electrode and the p-type gallium nitride layer, so that a relatively high threshold voltage of the transistor can be ensured, and a relatively high on-state current can be ensured at the same time, thereby improving the stability and electrical performance of the transistor.

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a barrier layer, a P-type gallium nitride layer, a cap layer, an etching groove, a source electrode and a drain electrode, the substrate, the barrier layer, the P-type gallium nitride layer, the cap layer and the etching groove are stacked in sequence, the source electrode and the drain electrode are arranged on the cap layer and far away from the two sides of the etching groove, and the etching groove penetrates through the cap layer and etches part of the P-type gallium nitride layer. A surface oxidation modified aluminum nitride deposition layer is arranged at the bottom of the etching groove, and a grid electrode is arranged on the surface oxidation modified aluminum nitride deposition layer. The semiconductor device provided by the invention not only can maintain relatively high conduction current, but also can enhance the threshold voltage performance of the device, and successfully improves the threshold voltage during zero bias on the premise of not sacrificing on-state current.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

The present invention discloses an N-polarity enhanced HEMT device structure and a preparation method thereof, wherein the structure comprises an N-polarity enhanced HEMT device body; a polarity neutralization composite gate structure is arranged between a channel layer and a gate of the N-polarity enhanced HEMT device body, wherein the polarity neutralization composite gate structure comprises a first polarity neutralization layer and a second polarity neutralization layer which are arranged in sequence from the channel layer to the gate and can combine with the channel layer to generate polarization charges, and the first polarity neutralization layer and the second polarity neutralization layer are made of different nitride materials. Thus, not only can the thickness of the polarity neutralization composite gate structure be ensured by the second polarity neutralization layer, the concentration of polarization charges for neutralizing two-dimensional electron gas can be increased, or the threshold voltage of the HEMT device can be increased by combining with the p-type doped polarity neutralization composite gate structure; but also the stress at the device gate can be reduced and the reliability of the device can be improved by adjusting the opposite stress of the first polarity neutralization layer and the second polarity neutralization layer.

The present invention provides an enhancement-mode gallium nitride device, a preparation method thereof and an electronic device. A composite gate structure in which a groove gate and a P-cap layer gate are arranged in a gate region along a gate length direction is provided to realize a three-dimensional structured gate. On the one hand, the threshold voltage of the gallium nitride device can be effectively improved to realize an enhancement-mode gallium nitride device. On the other hand, the groove gate can adjust its threshold voltage and the gate-source voltage point corresponding to the transconductance peak by changing the etching depth of the groove, so that the gate-source voltage points corresponding to the transconductance peaks corresponding to the groove gate and the P-cap layer gate are misaligned. When the transconductance of the P-cap layer gate is reduced, the transconductance value of the groove gate can be increased, and the transconductance values ​​of the P-cap layer gate and the groove gate are complemented, thereby realizing the overall transconductance half-peak width widening of the composite gate structure and improving the linearity of the enhancement-mode gallium nitride device.

The application discloses a threshold value adjustable vertical double diffusion metal oxide semiconductor field effect transistor, which comprises a drift region, a body region formed in the drift region from the upper surface of the drift region downwards, a gate oxide layer formed on the upper surfaces of the drift region and the body region, and a PN junction composite polysilicon gate formed on the upper surface of the gate oxide layer and composed of a first type polysilicon and a second type polysilicon, wherein the second type polysilicon covers all surfaces of the first type polysilicon except the bottom, and the vertical projection of the PN junction junction boundary formed by the first type polysilicon and the second type polysilicon is located in the body region in the channel region. When the transistor is turned on, the PN junction composite polysilicon gate is in a reverse bias state, and the threshold voltage is raised by affecting the inversion process of the body region through the junction electric field. The application realizes the raising of the threshold voltage of the device without weakening other performances of the device, and does not change the core gate oxide process and need to cooperate with a groove structure.

The invention discloses a longitudinal conduction normally-off type diamond power transistor and a preparation method thereof, and relates to the technical field of semiconductor power devices. The device comprises the following structures: a p-type low-resistance diamond single crystal substrate; the first p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond single crystal substrate; the p-type low-resistance diamond insertion layer is located on the upper surface of the first p-type high-resistance diamond drift layer; the second p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond insertion layer; and the p-type low-resistance diamond cap layer is located on the upper surface of the second p-type high-resistance diamond drift layer. The transistor provided by the invention is provided with the composite epitaxial layer with a multi-layer structure, wherein the low-resistance insertion layer can reduce the on resistance and improve the threshold voltage; and the high-resistance drift layer can bear higher voltage.

A display device includes: a first pixel driver to generate a control current; a second pixel driver to generate a driving current, and control a period during which the driving current flows, based on the control current; and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes: a first transistor to generate the control current based on a first data voltage; and a second transistor to provide the first data voltage to a first electrode of the first transistor based on a scan write signal from a scan write line. The second pixel driver includes: a third transistor to generate the driving current based on the control current; and a fourth transistor to provide a second data voltage to a first electrode of the third transistor based on a scan write signal from the scan write line.

The present invention provides a p-GaN HEMT device and a preparation method, a substrate layer; a buffer layer arranged on the substrate layer, a side of the buffer layer away from the substrate layer is provided with a P-type doping region; a channel layer arranged on the buffer layer, the channel layer is in contact with the P-type doping region; a barrier layer, a source electrode and a drain electrode arranged on the channel layer, the source electrode and the drain electrode are arranged on both sides of the barrier layer; a heat dissipation layer arranged on the barrier layer; a cap layer arranged on the barrier layer and on the heat dissipation layer; a passivation layer arranged on the heat dissipation layer, the passivation layer is arranged between the source electrode and the cap layer and between the drain electrode and the cap layer; a gate electrode arranged on the cap layer. The beneficial effects of the present invention are that the number of defects and the interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, the influence of interface reaction and defects on the working performance of the device can be reduced, the electric field at the 2DEG channel can be effectively modulated, the thermal management capability of the device itself can be improved, and the stability and reliability of the device operation can be improved.

The invention discloses a gallium nitride HEMT device and a preparation method thereof. The device comprises a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer, the channel layer and the barrier layer are sequentially arranged on the substrate; a two-dimensional electron gas channel is formed between the channel layer and the barrier layer; the two ends of the barrier layer are respectively provided with two epitaxial grooves, and the two epitaxial grooves extend into the channel layer so as to cut off the two-dimensional electron gas channels at the epitaxial grooves. The two tin oxide epitaxial layers respectively grow in the two epitaxial grooves; the source electrode and the drain electrode respectively grow on the two tin oxide epitaxial layers; the dielectric layer is arranged on the barrier layer and covers the surface, except the area where the two tin oxide epitaxial layers are located, of the barrier layer; and the gate electrode is arranged on the dielectric layer and is positioned between the source electrode and the drain electrode. The device provided by the invention has relatively small ohmic contact resistance, and can meet the application requirements of high-voltage and high-power electronic devices.

The invention relates to an epitaxial structure for an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a preparation method and application thereof, in particular to the field of power devices, and the epitaxial structure comprises a buffer layer, a first drift layer, a second drift layer, an AlN layer, a first NO-doped 3C-SiC layer, an O-doped 3C-SiC layer and a second NO-doped 3C-SiC layer which are sequentially arranged on a substrate. According to the epitaxial structure provided by the invention, the epitaxial structure is designed, and the specific design of the first NO-doped 3C-SiC layer, the O-doped 3C-SiC layer and the second NO-doped 3C-SiC layer is adopted, so that the defects of low channel mobility and over-low threshold voltage caused by poor SiO2 / SiC interface quality and high interface state are overcome; therefore, the obtained power device has excellent channel mobility and reasonable threshold voltage.

The invention provides a liquid crystal composition and a liquid crystal display device. The liquid crystal composition comprises at least one compound as shown in a general formula I, at least one compound as shown in a general formula II and at least one compound as shown in a general formula III. According to the liquid crystal composition disclosed by the invention, through mutual compounding of specific structures and contents of the compounds, the liquid crystal composition has proper vertical dielectric, proper dielectric anisotropy, relatively large optical anisotropy, relatively small rotary viscosity, shorter gray scale response time, relatively good low-temperature storage stability and relatively good Flicker value; the liquid crystal compound also has wider phase width to meet the display requirement at lower temperature, so that a liquid crystal display device comprising the liquid crystal compound has lower threshold voltage, higher response speed, higher contrast ratio and wider temperature use range. # imgabs0 #

The invention relates to the field of semiconductor device design and manufacturing, in particular to a semiconductor device structure and a forming method thereof. The method comprises the following steps: forming an injection mask on an epitaxial layer of a substrate, and respectively forming an N + region, a P well region, a P + region and a JFET region on the injection mask; forming a gate oxide layer; forming a polycrystalline silicon carbide film layer; performing P-type doping on the polycrystalline silicon carbide film layer; and carrying out patterning on the polycrystalline silicon carbide film layer after P-type doping so as to form a gate electrode. Compared with P-type polycrystalline silicon, the semiconductor device structure based on the P-type polycrystalline silicon carbide gate material can further improve threshold voltage, and other key characteristics such as on resistance are not sacrificed.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the first insulating layer is formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, two-dimensional charge carrier gas is formed at the interfaces of the fourth semiconductor layer and the first to third semiconductor layers. One of the following effects of simple device structure, simple process, low cost and excellent electrical performance can be realized.

The invention provides an organic electroluminescent material composition and an organic electroluminescent device comprising the same, the composition comprises a first compound shown in a chemical formula I and a second compound shown in a chemical formula II, a layer where the first compound is located is tightly attached to a layer where the second compound is located, the energy level of the composition is matched, and the energy level of the composition is matched with the energy level of the second compound. The absolute value of the energy range delta HOMO is small, and the hole mobility and the interface contact condition are good; the first compound provided by the invention is used as a hole transport layer, and the second compound is used as a light-emitting auxiliary layer to be applied to the organic electroluminescent device, so that the organic electroluminescent material composition can obviously reduce the driving voltage of the organic electroluminescent device, improve the current efficiency of the organic electroluminescent device, and improve the luminous efficiency of the organic electroluminescent device. According to the organic electroluminescent material composition provided by the invention, the service life of the organic electroluminescent device is prolonged, and the threshold voltage of the organic electroluminescent device can be improved, so that the crosstalk phenomenon is effectively avoided, and the defects in the prior art are overcome. [Chemical Formula I] # imgabs0 # [Chemical Formula II] # imgabs1 #

The invention belongs to the technical field of semiconductor devices, and particularly discloses a high-electron-mobility transistor with an InGaN insertion layer and a double-barrier cap layer and a preparation method of the high-electron-mobility transistor. The high-electron-mobility transistor comprises a substrate, a nucleating layer, an AlGaN gradient buffer layer, a GaN channel layer, an InGaN insertion layer, an AlGaN barrier layer, a barrier protection layer, a double-barrier cap layer (an AlGaN layer, a GaN layer and an AlGaN layer) and a gate electrode which are sequentially arranged in a contact mode. Ohmic contact regions are arranged on the two sides of the AlGaN barrier layer and the barrier protection layer respectively and are electrically connected with the source electrode and the drain electrode respectively. By introducing the specific epitaxial layer combination and doping design, the distribution and control of two-dimensional electron gas are optimized, the confinement to electrons is increased, the output characteristic of the device is improved, the current collapse effect is inhibited, the leakage current is reduced, and the threshold voltage stability and switching characteristic of the device are improved.

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a semiconductor material layer; forming a first mask layer, wherein the first mask layer forms a first opening exposing the first region of the semiconductor material layer and at least shields the second region of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region of the first conductive type; forming a second mask layer which forms a second opening exposing the second area and at least shields the first area; performing a second ion implantation process on the second region based on the second mask layer to form a first well region of the first conductive type; the second injection concentration of the second ion injection process is greater than the first injection concentration of the first ion injection process; forming a second drift region of a second conductive type; a first source region and a first drain region are respectively formed in the first well region and the second drift region. Therefore, the influence on the threshold voltage is reduced while the hot carrier effect is improved.

The invention discloses a Pocket doped 4H-SiC-based avalanche photodiode device. The Pocket doped 4H-SiC-based avalanche photodiode device comprises a substrate layer, a multiplication layer, a passivation layer, a PAD layer, a metal electrode region and a photosensitive window region. A Pocket highly-doped region is introduced into a multiplication layer of the 4H-SiC avalanche photodiode, so that the electric field distribution condition at the edge of a boss surface of the multiplication layer is optimized, the breakdown probability of the boss surface is reduced, the available carrier concentration of the multiplication region is increased, the light current is increased while the lower dark current is kept, the threshold voltage of the device is increased, and the device performance is improved. The current gain and the signal-to-noise ratio are increased, and good photoelectric amplification performance is shown.

The present invention relates to the technical field of vacuum micro-nanoelectronics, and more specifically, to an addressable flat-panel X-ray source driven by a high-voltage TFT and a preparation method thereof. The high-voltage TFT comprises a bottom gate electrode and a top gate electrode. An active layer arranged on the top of a gate insulating layer comprises a plurality of parallel channels, and a gap is formed between adjacent channels. The bottom gate electrode and the top gate electrode together form a double-gate structure, which enhances the regulation effect on the gate-controlled channel of the high-voltage TFT, can effectively improve the threshold voltage and subthreshold swing of the high-voltage TFT, and increase the saturation current; the gap between adjacent channels can enhance the heat dissipation effect, ensure that the device will not have the problem of thermal breakdown, and the parallel channel structure enables the double-gate high-voltage TFT to achieve a large current while ensuring its withstand voltage performance, thereby meeting the requirements of the flat-panel X-ray source for a high operating voltage and a large operating current of a driving unit, and realizing an addressable flat-panel X-ray source with high voltage, large current, high resolution and accurate current regulation.