8results about How to "Raise the threshold voltage" patented technology

The invention discloses a p-channel gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The p-channel gallium nitride transistor comprises a substrate; the barrier layer and the p-type gallium nitride layer are located on one side of the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; the p-type gallium nitride layer comprises a first groove, and a first bulge and a second bulge which are positioned on two opposite sides of the first groove; the ratio range of the thickness L1 of the groove bottom of the first groove to the thickness L2 of the p-type gallium nitride layer at the first bulge and / or the second bulge is 1 / 14 < = L1 / L2 < = 3 / 14; a depletion layer located in the first groove; the depletion layer comprises a titanium metal layer and a titanium nitride layer which are laminated, and the titanium nitride layer is located between the titanium metal layer and the p-type gallium nitride layer; the source electrode and the drain electrode are located on the sides, away from the substrate, of the first protrusion and the second protrusion respectively; the grid electrode is located in the first groove and located on the side, away from the p-type gallium nitride layer, of the depletion layer. The stability and the electrical performance of the transistor are improved.

This invention discloses a method for manufacturing a trench gate semiconductor power device, comprising: forming a first hard mask layer on a first epitaxial layer; patterning and etching the first hard mask layer to open the formation region of the gate trench; etching the first epitaxial layer to form the gate trench; removing the first hard mask layer and then performing a first thermal oxidation process to form a first field oxide layer on the inner surface and outer surface of the gate trench; performing a first CVD growth process to form a second field oxide layer, and stacking the first and second field oxide layers to form a third field oxide layer; performing a first CMP process to remove the third field oxide layer outside the gate trench; forming a first polysilicon layer to completely fill the gate trench and extend it outside the gate trench; and performing a second CMP process to planarize the first polysilicon layer. This invention can simultaneously improve the structural consistency of the gate trench region and the plateau region, and can comprehensively improve the device performance and yield.

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.

The application discloses a threshold value adjustable vertical double diffusion metal oxide semiconductor field effect transistor, which comprises a drift region, a body region formed in the drift region from the upper surface of the drift region downwards, a gate oxide layer formed on the upper surfaces of the drift region and the body region, and a PN junction composite polysilicon gate formed on the upper surface of the gate oxide layer and composed of a first type polysilicon and a second type polysilicon, wherein the second type polysilicon covers all surfaces of the first type polysilicon except the bottom, and the vertical projection of the PN junction junction boundary formed by the first type polysilicon and the second type polysilicon is located in the body region in the channel region. When the transistor is turned on, the PN junction composite polysilicon gate is in a reverse bias state, and the threshold voltage is raised by affecting the inversion process of the body region through the junction electric field. The application realizes the raising of the threshold voltage of the device without weakening other performances of the device, and does not change the core gate oxide process and need to cooperate with a groove structure.

A display device includes: a first pixel driver to generate a control current; a second pixel driver to generate a driving current, and control a period during which the driving current flows, based on the control current; and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes: a first transistor to generate the control current based on a first data voltage; and a second transistor to provide the first data voltage to a first electrode of the first transistor based on a scan write signal from a scan write line. The second pixel driver includes: a third transistor to generate the driving current based on the control current; and a fourth transistor to provide a second data voltage to a first electrode of the third transistor based on a scan write signal from the scan write line.

The invention belongs to the technical field of semiconductor devices, and particularly discloses a high-electron-mobility transistor with an InGaN insertion layer and a double-barrier cap layer and a preparation method of the high-electron-mobility transistor. The high-electron-mobility transistor comprises a substrate, a nucleating layer, an AlGaN gradient buffer layer, a GaN channel layer, an InGaN insertion layer, an AlGaN barrier layer, a barrier protection layer, a double-barrier cap layer (an AlGaN layer, a GaN layer and an AlGaN layer) and a gate electrode which are sequentially arranged in a contact mode. Ohmic contact regions are arranged on the two sides of the AlGaN barrier layer and the barrier protection layer respectively and are electrically connected with the source electrode and the drain electrode respectively. By introducing the specific epitaxial layer combination and doping design, the distribution and control of two-dimensional electron gas are optimized, the confinement to electrons is increased, the output characteristic of the device is improved, the current collapse effect is inhibited, the leakage current is reduced, and the threshold voltage stability and switching characteristic of the device are improved.

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a semiconductor material layer; forming a first mask layer, wherein the first mask layer forms a first opening exposing the first region of the semiconductor material layer and at least shields the second region of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region of the first conductive type; forming a second mask layer which forms a second opening exposing the second area and at least shields the first area; performing a second ion implantation process on the second region based on the second mask layer to form a first well region of the first conductive type; the second injection concentration of the second ion injection process is greater than the first injection concentration of the first ion injection process; forming a second drift region of a second conductive type; a first source region and a first drain region are respectively formed in the first well region and the second drift region. Therefore, the influence on the threshold voltage is reduced while the hot carrier effect is improved.

This invention belongs to the field of power semiconductor technology and relates to a lateral enhancement-mode gallium oxide transistor with a selectively recessed current blocking region. At zero bias, the current blocking region, combined with the depletion effect of the P-type semiconductor layer on the channel, achieves enhancement-mode functionality and increases the threshold voltage. During forward conduction, the selective recess and P-type semiconductor layer increase channel density, and the channel sidewalls form an electron accumulation layer conductive path, reducing on-resistance and increasing current capability. During forward blocking, the current blocking region suppresses leakage current, and the toothed heterogate stepped field plate, combined with the patterned source field plate and drain region stepped doping, alleviates electric field concentration and optimizes electric field distribution in the lateral, longitudinal, and vertical directions, thereby improving the device breakdown voltage. The beneficial effects of this invention are that the device possesses high threshold voltage, low on-resistance, and high breakdown voltage.