53results about How to "Reduced Junction Leakage Current" patented technology

A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.

A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

The invention provides a transistor forming method. The transistor forming method comprises the following steps of: providing a substrate; forming a well region in the substrate; forming a gate structure on the surface of the substrate, wherein the gate structure comprises a gate oxide layer and a gate positioned on the surface of the gate oxide layer; forming a source region and a drain region which are positioned in the substrate on the two sides of the gate structure; and after forming the source region and the drain region, doping first ions in the substrate to adjust a threshold voltage. The first ions for adjusting the threshold voltage are injected after the formation of the source region and the drain region, so that the influence on the diffusion of the first ions caused by a heat treatment process before injecting the first ions is reduced; most of the first ions are distributed close to the surface of the substrate; the concentration of the first ions diffused in the substrate is reduced; the junction capacitance between the source region / drain region and the substrate is reduced; the junction drain current is reduced; the operation speed of a device is increased; and the performance of the device is improved.

A method for manufacturing a MOS transistors in a semiconductor device includes the step of implanting a dopant in a channel layer or source / drain regions by using a multi-step implantation and an associated multi-step heat treatment, wherein the multi-step implantation includes a number of steps of implantation each for implanting the dopant at a dosage lower than 1x1013 / cm2. The total dosage of the multi-step implantation ranges between 1x1013 / cm2 and 3x1013 / cm2.

A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

The present invention provides integrated circuit structures. The above-mentioned integrated circuit structure includes a base and a channel on the base. The channel includes a first group III-V compound semiconductor material composed of group III elements and group V elements. A gate structure is disposed on the channel. A source / drain region adjoins the channel, and the source / drain region includes a Group IV region selected from a group consisting essentially of silicon, germanium, and combinations thereof. By regrowing Si / Ge source / drain regions, existing silicidation techniques can be used to reduce source / drain resistance and improve final transistor drive current. The buffer layer has the effect of moderating the lattice constant transition between the channel and source / drain regions of the transistor, thus resulting in a reduced defect density and reduced junction leakage.

The invention provides a transistor and a manufacturing method for the same. The method includes the steps: providing a semiconductor substrate with a formed active layer; forming buried layers spaced from the active layer on the surface of the semiconductor substrate on two sides of the active layer; forming first epitaxial layers flush with the active layer on the surfaces of the buried layers and in the space between each buried layer and the active layer; forming grooves exposed out of the semiconductor substrate in the first epitaxial layers, wherein the grooves are positioned among the buried layers and the active layer; forming buried side walls in the grooves, wherein the thickness of each buried side wall is smaller than the depth of each groove; forming second epitaxial layers on the surfaces of the buried side walls, the active layer and the first epitaxial layers; forming gate structures on the surfaces of the second epitaxial layers above the active layer; and forming a source region and a drain region in the second epitaxial layer and the first epitaxial layer on two sides of each gate structure, wherein the source region and the drain region are positioned on two sides of an isolating side wall. By the aid of the method, the short-channel effect and the performance of the transistor are improved.

Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.

The invention discloses a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the steps as follows: a first ion implantation process is carried out on a substrate in a PMOS peripheral region at two sides of a first gate structure and a first graded junction region is formed at the lower part of a first peripheral source-drain region; a second ion implantation process is carried out on the first peripheral source-drain region and a first core drain-source region, and a first contact resistance region is formed on the surface of the first peripheral source-drain region and the surface of the first core drain-source region; a third ion implantation process is carried out on the substrate in an NMOS peripheral region at two sides of a third gate structure and a second graded junction region is formed at the lower part of a second peripheral source-drain region; and a fourth ion implantation process is carried out on a second peripheral source-drain region and a second core drain-source region, and a second contact resistance region is formed on the surface of the second peripheral source-drain region and the second core drain-source region. According to the semiconductor device, the problem of a short channel effect of a core device is solved while junction leakage current of an input / output device is reduced, thereby improving the electric property of the formed semiconductor device.

An MOS transistor comprises low doped source / drain extended regions in a semiconductor substrate and on two sides of a grid structure, sidewalls located on the semiconductor substrate on two sides of the grid structure, heavily doped source / drain regions located in the semiconductor and on two sides of the grid structure, and pocket regions and F-ion doped regions respectively located in the semiconductor substrate and on two sides of the grid structure, wherein the F-ion doped regions are located around the pocket regions. The invention further provides a method of forming the MOS transistors. By forming the F-ion doped regions around the pocket regions of the MOS transistor, transient enhanced diffusion effect of ions from the pocket regions into the semiconductor substrate can be prevented, thereby reducing junction depth, decreasing junction current leakage, and improving the performance of the MOS transistor.

The invention relates to a semiconductor structure and a manufacturing method thereof. The method comprises the steps of providing a base, wherein the base comprises a first depth region, a second depth region and a third depth region; forming a buffer doping ion region in the base of the second depth region; removing a part of the base of the second depth region and the third depth region to form a substrate and fin parts protruding out of the substrate; forming an isolation structures with thickness equal to the depth of the second depth region on the substrate, wherein the fin part exposed out of the isolation structure is a fin part first region, and a part which is not exposed is a fin part second region; forming a punchthrough-prevention doping ion region with an ion type same as that of the buffer doping ion region in the fin part second region, wherein the ion concentration of the punchthrough-prevention doping ion region is larger than that of the buffer doping ion region; forming a grid structure bridging the fin parts; and forming a source-drain doping region in the fin part first region at two sides of the grid structure. The ion concentration of the punchthrough-prevention doping ion region is between that of the source-drain doping region and that of the buffer doping ion region, and thus, the junction leak current between the source-drain doping region and the substrate is reduced.