52results about How to "Reduced Junction Leakage Current" patented technology

A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof. By re-growing silicon/germanium source/drain regions, the existing silicidation technique can be used to reduce the source/drain resistance and to improve drive currents of the resulting transistors. Buffer layers have the effect of smoothening the lattice constant transition between the channel of the transistor and the source/drain regions, resulting in a reduced defect density and reduced junction leakage currents.

The invention discloses a semiconductor structure forming method. The method comprises steps: a substrate is provided, wherein the substrate comprises a first area and a second area, surfaces of the first area and the second area of the substrate are provided with pseudo gate structures respectively, and the pseudo gate structure comprises a pseudo gate layer and an initial mask layer located on the surface of the pseudo gate layer; a first stress layer is formed in the substrate at two sides of the pseudo gate structure in the first area; a first deep injection process is adopted to dope ions of a first type in the first stress layer and in the partial substrate at the bottom part of the first stress layer; after the first deep injection process, the thickness of the initial mask layer is thinned, and a first mask layer is formed; a second source-drain area is formed in the substrate at two sides of the pseudo gate structure in the second area; and after the first mask layer and the second source-drain area are formed, a dielectric layer is formed on the surface of the substrate, the dielectric layer covers the side wall surface of the pseudo gate structure, and the surface of the dielectric layer is flush with the top surface of the first mask layer. The performance of the formed semiconductor structure is improved.

An MOS transistor comprises low doped source/drain extended regions in a semiconductor substrate and on two sides of a grid structure, sidewalls located on the semiconductor substrate on two sides of the grid structure, heavily doped source/drain regions located in the semiconductor and on two sides of the grid structure, and pocket regions and F-ion doped regions respectively located in the semiconductor substrate and on two sides of the grid structure, wherein the F-ion doped regions are located around the pocket regions. The invention further provides a method of forming the MOS transistors. By forming the F-ion doped regions around the pocket regions of the MOS transistor, transient enhanced diffusion effect of ions from the pocket regions into the semiconductor substrate can be prevented, thereby reducing junction depth, decreasing junction current leakage, and improving the performance of the MOS transistor.

A method for manufacturing a MOS transistors in a semiconductor device includes the step of implanting a dopant in a channel layer or source/drain regions by using a multi-step implantation and an associated multi-step heat treatment, wherein the multi-step implantation includes a number of steps of implantation each for implanting the dopant at a dosage lower than 1×10¹³/cm². The total dosage of the multi-step implantation ranges between 1×10¹³/cm² and 3×10¹³/cm².

A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.

The invention provides an MOS transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor substrate; carrying out non-crystallization ion implantation on the semiconductor substrate, and forming a non-crystallization region in the semiconductor substrate; carrying out threshold voltage injection on the semiconductor substrate, and forming a threshold voltage injection region on the non-crystallization region; forming a gate structure at a semiconductor substrate surface above the threshold voltage injection region; forming a source/drain region in the semiconductor substrate at two sides of the gate structure. According to the MOS transistor and the manufacturing method in the invention, junction capacitance of the MOS transistor is reduced, a response speed of the MOS transistor is raised, and leakage current of the MOS transistor is reduced.

The invention discloses a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the steps as follows: a first ion implantation process is carried out on a substrate in a PMOS peripheral region at two sides of a first gate structure and a first graded junction region is formed at the lower part of a first peripheral source-drain region; a second ion implantation process is carried out on the first peripheral source-drain region and a first core drain-source region, and a first contact resistance region is formed on the surface of the first peripheral source-drain region and the surface of the first core drain-source region; a third ion implantation process is carried out on the substrate in an NMOS peripheral region at two sides of a third gate structure and a second graded junction region is formed at the lower part of a second peripheral source-drain region; and a fourth ion implantation process is carried out on a second peripheral source-drain region and a second core drain-source region, and a second contact resistance region is formed on the surface of the second peripheral source-drain region and the second core drain-source region. According to the semiconductor device, the problem of a short channel effect of a core device is solved while junction leakage current of an input/output device is reduced, thereby improving the electric property of the formed semiconductor device.

The invention relates to a preparation method of a semiconductor device, and the method comprises the steps: obtaining a substrate, and forming a gate structure on the substrate; first ion implantation is carried out on the substrate, and pre-amorphization regions are formed on the two sides of the gate structure; second ion implantation is carried out on the pre-amorphization area, and an amorphization area is formed in the pre-amorphization area; forming first side walls on two sides of the gate structure; performing a second doping process, and forming a second doped region in the non-crystallization region; second side walls are formed on the two sides of the first side walls; and forming a heavily doped source region and a heavily doped drain region in the second doped region. Transverse diffusion and longitudinal diffusion of doped ions in the second doped region are inhibited, and the effective distance between the heavily doped drain region and the edge of the drain region is increased, so that the junction leakage current is reduced.

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; a gate structure disposed on the surface of the substrate; a lightly doped region arranged in the substrate on the two sides of the gate structure and extending to be below the gate structure; an L-shaped groove and a stress layer in the L-shaped groove. The L-shaped groove is arranged in the substrate on the two sides of the gate structure. One part of the stress layer is arranged below the lightly doped region. The stress layer below the lightly doped region is of a cuboid structure. In this way, the formation of a tip structure between the stress layer and the substrate is avoided, so that the junction leakage current caused by the tip structure is avoided. Meanwhile, below a conductive channel, the stress layer of the cuboid structure is away from the conductive channel compared with a sigma-type stress layer. Therefore, the stress below the conductive channel is reduced, and the junction leakage current is further reduced.

The invention discloses a semiconductor structure based on low-temperature ion implantation, transistor preparation and a semiconductor processing device. The method comprises the steps of: providinga to-be-processed structure, and defining an ion implantation layer region with an ion implantation surface; cooling the to-be-processed structure, performing ion implantation from the ion implantation surface, wherein in the ion implantation process, an ion implantation layer area is converted into a recovery damage crystallization layer area and a lattice damage amorphous layer area, the self-annealing effect in the ion implantation layer area is relieved through cooling treatment, and the size of the recovery damage crystallization layer area is reduced; and performing annealing treatment,converting the lattice damage amorphous layer area into a recrystallization layer area, and converting the recovery damage crystallization layer area into a crystallization defect layer area. The to-be-processed structure is cooled in the ion implantation process, ion implantation is carried out under the low-temperature condition, and the self-annealing effect in the ion implantation process is relieved, so that the EOR defect after annealing is reduced, the junction leakage current is reduced, and the power consumption of an electronic device is reduced.