Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. The method includes the following steps: providing a semiconductor substrate, and forming a gate stacking structure on the surface of the semiconductor substrate; etching the semiconductor substrate by using the gate stacking structure as a mask so as to form grooves in the semiconductor substrate on the two sides of the gatestacking structure; forming buffer diffusion layers surrounding the corresponding grooves on at least one side of the gate stacking structure; and forming a source electrode and a drain electrode inthe grooves. According to the method of the invention, the buffer diffusion layers are formed before forming the source electrode and the drain electrode, diffusion of impurities in the buffer diffusion layers drives diffusion of impurities in the source electrode and drain electrode regions in a subsequent annealing process, and so the distribution of the impurities in the source electrode and the drain electrode regions more uniform, the electric field distribution of PN junctions of the source electrode and the drain electrode regions is reduced, lateral diffusion of the impurities can be avoided, lateral short channel effect is controlled, the junction capacitance and the junction leakage current of the source electrode and the drain electrode regions are reduced, and the yield rate and performance of the semiconductor device are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] As the feature size of metal-oxide-semiconductor (metal oxide semiconductor, MOS) field effect transistor devices continues to decrease, it becomes more and more important to effectively control the channel length of MOS devices during their fabrication. challenge. For this reason, the short-channel effect of core devices can be improved by adopting the method of forming ultra-shallow junctions and abrupt junctions in MOS devices. However, in the process of forming ultra-shallow junctions and abrupt junctions, how to find a more reasonable balance between suppressing the Short Channel Effect (SCE) and improving the performance of MOS devices is also an extremely challenging task. [0003] In order to further improve the performance of MOS devices, those skilled in the art are devoting themse...

AI Technical Summary

Problems solved by technology

However, while these methods improve the short channel effect, they will lead to an increase in junction leakage current, which in turn leads to a decrease in the performance of semiconductor devices.

Images