103results about How to "Avoid lateral spread" patented technology

Disclosed is an absorbent article including a backsheet, an absorbent storage layer, a liquid guide layer, and a top layer. The absorbent storage layer, the liquid guide layer and the top layer satisfy the following relationships: the liquid guide layer>the absorbent storage layer>the top layer with respect to a water absorbency due to capillary phenomenon; the liquid guide layer>the absorbent storage layer>the top layer with respect to a retention ratio of a liquid dropped onto the top layer in an amount less than a maximum water absorption amount of the liquid guide layer; and the absorbent storage layer>the liquid guide layer>the top layer with respect to a retention ratio of a liquid dropped onto the top layer in an amount more than the maximum water absorption amount of the liquid guide layer.

The invention relates to one-time sintered super-flat ink-jet penetrating porcelain tiles with three-dimensional decorative effects, and a manufacturing method thereof. According to the manufacturing method, a bottom green brick layer, a priming glaze slurry, a semitransparent glaze slurry, and a transparent glaze slurry are prepared respectively; the bottom green brick layer is subjected to following treatment respectively: a priming glaze layer is formed via priming glaze slurry pouring, jet printing of decorative patterns is carried out, a semitransparent glaze layer is formed via semitransparent glaze slurry pouring, and drying is carried out; obtained green bricks are printed with decorative patterns with ink-jet of penetrating ink and jet printing of a permeation promoter, and are allowed to stand for more than 5min; the obtained green bricks are printed with isolation glaze with water isolating performance via silk-screen printing, and are dried and cooled; the green bricks are coated with the transparent glaze slurry via pouring; the green bricks are subjected to one time sintering so as to obtain one-time sintered ink-jet penetrating porcelain tile semi-finished products with three-dimensional decorative effects; the semi-finished products are subjected to polishing via inelastic module technology so as to obtain the one-time sintered super-flat ink-jet penetrating porcelain tiles with three-dimensional decorative effects.

A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.

The present invention relates to high-throughput systems and methods to prepare a large number of component combinations, at varying concentrations and identities, at the same time, and high-throughput methods to test tissue barrier transfer, such as transdermal transfer, of components in each combination. The methods of the present invention allow determination of the effects of inactive components, such as solvents, excipients, enhancers, adhesives and additives, on tissue barrier transfer of active components, such as pharmaceuticals. The invention thus encompasses the high-throughput testing of pharmaceutical compositions or formulations in order to determine the overall optimal composition or formulation for improved tissue transport, such as transdermal transport.

Disclosed is a sanitary napkin which is allowed to quickly absorb menstrual blood and also effective in preventing absorbed menstrual blood from returning to the skin-side surface under pressure and in concealing the color of absorbed menstrual blood from the outside. Between a liquid absorbent layer and a topsheet formed of a resin film having a large number of liquid passage apertures, there is disposed a barrier layer formed of a resin film having a large number of liquid passage apertures. The barrier layer is composed of a plurality of strip-shaped elements, and liquid passage regions are defined between adjacent elements of the barrier layer. After passing through the liquid passage apertures of the topsheet, menstrual blood tends to be absorbed by the liquid absorbent layer through the liquid passage regions. The barrier layer functions to prevent liquid return and conceal the color of menstrual blood.

A method for connecting substrates having electrical conductive elements thereon, comprising: providing at least one spacer between the substrates; applying a conductive material to at least one of the electrical conductive elements; aligning the electrical conductive elements; and, connecting the substrates by urging them together, wherein the at least one spacer prevents lateral spreading of the conductive material on the substrates from bridging a distance between adjacent conductive elements during the connecting.

The invention relates to matt color ink jet printer paper paint and a preparation method thereof. The preparation method is characterized in that the method comprises the following steps: adding dispersant into deionized water to be dissolved at the room temperature; adding modified bentonitic clay to the dissolved deionized water and dispersing at the room temperature; adding silicon dioxide to the modified bentonitic clay dispersion liquid for dispersion, and obtaining mixed dispersion liquid; adding an adhesion agent to the mixed dispersion liquid while stirring; adding a silicone antifoaming agent, PDMDAAC and carboxymenthyl cellulose in sequence, and obtaining paint liquid after evenly blending and stirring. Because the modified bentonitic clay is utilized as the pigment to prepare the paint for the matt color ink jet printer paper, good water absorption performance, good color fixation performance, high color density, good color reductibility and no infiltration of the matt color ink jet printer paper can be ensured, and the purpose of reducing the cost of the matt color ink jet printer paper can be achieved.

The present invention relates to a mechanism for bedding a receiver frame (3) and/or a barrel (1) in a stock (2) of a firearm, the mechanism having a bearing component (8) which can be attached to the stock (2) and which, on its upper surface, has a bearing surface (10,11) for bearing the receiver frame (3) and/or the barrel (1). To ensure permanent and reproducibly accurate positioning, the lower surface of the bearing component (8) comprises a guide profile (9) for seating the bearing component (8) free from play in the stock (2).

The present invention relates to a semiconductor component and a method for manufacturing the same. The semiconductor component comprises a semiconductor body, which includes a substrate of a first conducting type, a buried semiconductor layer of a second conducting type being arranged on the substrate, a functional cell semiconductor layer of a third conducting type being arranged on the buried semiconductor layer. The functional cell semiconductor layer provides at least two semiconductor functional cells being arranged landscape orientation in a row. The buried semiconductor layer is part of at least one semiconductor functional cell. The semiconductor functional cells are electrically insulated with each other by means of the functional semiconductor layer, the buried semiconductor layer and the separating structure of the substrate. The separating structure comprises at least a trench and a conducting contact with the substrate, the contact is electrically insulated with the functional cell semiconductor layer and the buried layer by means of at least one trench.

Provided is a semiconductor device and a method of manufacturing a semiconductor device. In the semiconductor device, high-concentration n type impurity regions are formed respectively below gate electrodes. By setting a gate length to be smaller than a depth of channel regions, pn junction interfaces formed of adjacent side faces of the n type impurity regions and the channel regions can be substantially vertical to a top surface of a base. With this configuration, even when reduction in size is achieved in a super junction structure, a distance between the channel regions (i.e. a current path below the gate electrode) is not reduced unnecessarily. Accordingly, an increase in resistance can be prevented. In addition, depletion layers uniformly expand in the n type semiconductor regions, and impurity concentration of the regions can be increased consequently. Accordingly, reduction in resistance can be achieved.

Disclosed is a sanitary napkin which is allowed to quickly absorb menstrual blood and also effective in preventing absorbed menstrual blood from returning to the skin-side surface under pressure and in concealing the color of absorbed menstrual blood from the outside. Between a liquid absorbent layer and a topsheet formed of a resin film having a large number of liquid passage apertures, there is disposed a large number of barrier members having a small width. The barrier members are strips formed of a resin film, and gaps are left between adjacent barrier members. After passing through the liquid passage apertures of the topsheet, menstrual blood tends to be absorbed by the liquid absorbent layer through the gaps. The barrier members also function to prevent liquid return and conceal the color of menstrual blood.

The invention discloses a slapper energy change element structure and a preparation method thereof. The slapper energy change element structure comprises a shear layer, a fly layer, an explosive foil and a substrate, wherein the shear layer, the fly layer, the explosive foil and the substrate are laminated and bonded in sequence from top to bottom; a plurality of conductive through holes are formed in the substrate in a penetrating manner; the hole surfaces of the upper ends of the conductive through holes are in contact with the lower surface of the explosive foil; the hole surfaces of the lower ends of the conductive through holes are flush with the lower surface of the substrate; a shear through hole is formed in the center of the shear layer in a penetrating manner; the upper hole surface of the shear through hole is flush with the upper surface of the shear layer; the lower hole surface of the shear through hole is in contact with the upper surface of the fly layer; and the fly layer is made of a polyimide material. By lamination and bonding of the shear layer, the fly layer, the explosive foil and the substrate in sequence from top to bottom, contact of the molecular layers of the substrate, the explosive foil and the fly layer is realized, and transverse diffusion of plasmas is prevented, so that the energy conversion efficiency is improved.

The invention provides a preparation method of a static random access memory. According to the preparation method, pre-amorphization ion implantation is performed on a part of a polycrystalline silicon layer before N-type ion implantation is performed, so that the condition that implanted ions longitudinally diffuse, penetrates a gate oxide layer and enters a P well region due to overlarge grain size in the polycrystalline silicon layer in the N-type ion implantation process can be prevented, so that the reduction of the threshold voltage of a subsequently formed pull-down NMOS transistor caused by the above condition can be avoided, and the voltage mismatch can be avoided; meanwhile, the inhibition effect of N-type ion implantation on a polycrystalline depletion effect is improved; and besides, a pull-up PMOS transistor and a pull-down NMOS transistor which are formed subsequently share the same gate structure, so that transverse diffusion of ions in the N-type ion implantation can be inhibited by executing the pre-amorphization ion implantation, the influence of the N-type ion implantation on the threshold voltage of the pull-up PMOS transistor formed subsequently is avoided, and the problem of voltage mismatch is relieved, and device performance can be improved. The same mask is used for two times of ion implantation, and therefore, the preparation cost is low, and the process is simple.

A method for forming a transistor, comprising: providing a semiconductor substrate, forming a gate dielectric layer and a gate electrode on the gate dielectric layer on the semiconductor substrate, and the gate electrode includes a first gate electrode on the gate dielectric layer layer and a second gate layer located on the first gate layer, the material of the first gate layer is different from the material of the second gate layer; a part of the width is etched along the sidewall of the first gate layer Openings are formed on both sides of the remaining first gate layer at the bottom of the second gate layer; after the openings are formed, the first ion implantation is performed using the gate electrode as a mask, and on both sides of the gate electrode A lightly doped region is formed in the semiconductor substrate; after the opening is formed, the gate electrode is used as a mask to perform an angled second ion implantation, and a pocket-shaped implanted region is formed in the semiconductor substrate at the bottom of the gate electrode. The pocket-shaped implanted region The doping type of the region is opposite to that of the shallowly doped region. The transistor formed by the method of the invention can better prevent the generation of short channel effect.

The invention provides a three-dimensional memory and a preparation method thereof. The method comprises the following steps: forming a laminated structure on a substrate, wherein the laminated structure comprises gate sacrificial layers and gate layers which are alternately laminated; forming a channel hole penetrating through the laminated structure and extending to the substrate, and sequentially forming a barrier layer, a charge capture layer, a tunneling layer and a channel layer on the inner wall of the channel hole to form a channel structure; forming a gate groove penetrating through the laminated structure and extending to the substrate, and forming a gap between the gate groove and the channel structure; sequentially removing the gate sacrificial layer, the part, corresponding to the gate sacrificial layer, of the barrier layer and the part, corresponding to the gate sacrificial layer, of the charge trapping layer through the gate groove to form a sacrificial gap; and filling a dielectric material in the sacrificial gap to form a gate dielectric layer. According to the preparation method, lateral diffusion of the charge trapping layer corresponding to each gate layer can be effectively inhibited, and the storage reliability of the charge trapping layer is improved, so that the storage retention characteristic of the prepared three-dimensional memory is improved.