Three-dimensional memory and preparation method thereof

A memory, three-dimensional technology, applied in the direction of semiconductor devices, electric solid-state devices, electrical components, etc., can solve the problems of reducing the retention of three-dimensional memory and reducing the storage reliability of the charge trapping layer

Pending Publication Date: 2021-05-18
YANGTZE MEMORY TECH CO LTD
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  • Abstract
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  • Claims
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Problems solved by technology

However, during the storage process, the charges stored in the charge traps will diffuse toward the axial direction of the channel structure, which will reduce the s

Method used

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  • Three-dimensional memory and preparation method thereof
  • Three-dimensional memory and preparation method thereof
  • Three-dimensional memory and preparation method thereof

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[0026] For a better understanding of the application, various aspects of the application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are descriptions of exemplary embodiments of the application only, and are not intended to limit the scope of the application in any way.

[0027] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms "comprises", "includes", "includes" and / or "includes" indicate the presence of said features, integers, elements, components and / or combinations thereof, but do not exclude The presence of one or more other features, integers, elements, components and / or combinations thereof.

[0028] The description herein is made with reference to schematic illustrations of exemplary embodiments. Exemplary embodiments disclosed herein should not be constru...

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Abstract

The invention provides a three-dimensional memory and a preparation method thereof. The method comprises the following steps: forming a laminated structure on a substrate, wherein the laminated structure comprises gate sacrificial layers and gate layers which are alternately laminated; forming a channel hole penetrating through the laminated structure and extending to the substrate, and sequentially forming a barrier layer, a charge capture layer, a tunneling layer and a channel layer on the inner wall of the channel hole to form a channel structure; forming a gate groove penetrating through the laminated structure and extending to the substrate, and forming a gap between the gate groove and the channel structure; sequentially removing the gate sacrificial layer, the part, corresponding to the gate sacrificial layer, of the barrier layer and the part, corresponding to the gate sacrificial layer, of the charge trapping layer through the gate groove to form a sacrificial gap; and filling a dielectric material in the sacrificial gap to form a gate dielectric layer. According to the preparation method, lateral diffusion of the charge trapping layer corresponding to each gate layer can be effectively inhibited, and the storage reliability of the charge trapping layer is improved, so that the storage retention characteristic of the prepared three-dimensional memory is improved.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and more specifically, to a three-dimensional storage device and a manufacturing method thereof. Background technique [0002] Three-dimensional memory (3D NAND) increases storage density by using vertical memory arrays. The manufacturing process of the three-dimensional memory mainly includes: first forming a channel hole in a laminated structure in which the gate dielectric layer and the gate layer are alternately stacked, and then depositing a functional layer and a channel layer in sequence in the channel hole to form a memory function. channel structure. [0003] The functional layer in the channel structure is the key structure for the three-dimensional memory to complete the storage function. Specifically, the functional layer includes a silicon oxide-silicon nitride-silicon oxide (ONO) structure sequentially formed on the outer wall of the channel structure, and each ga...

Claims

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Application Information

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IPC IPC(8): H01L27/11582H01L27/1157
CPCH10B43/35H10B43/27
Inventor 高庭庭夏志良刘小欣孙昌志耿万波杜小龙
Owner YANGTZE MEMORY TECH CO LTD
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