31results about How to "Improve leakage performance" patented technology

A calibration system of architecture, apparatus, algorithms and method for optimizing leakage performance of a multi-port amplifier (MPA) for satellite communications. The calibration system comprises simple onboard apparatus and generally on-ground algorithms implementation connected via telecommand and telemetry links. The isolation performance of the MPA is monitored by using a commandable frequency generator and a flexible narrowband receiver. The high performance is achieved by direct and efficient optimization of the aggregate leakage of the MPA. The calibration system may be applied but not limited to Ku and Ka-band high throughput satellite systems.

The invention belongs to the technical field of super-large-scale integrated circuits and particularly relates to a super-low k material thin film and a preparation method thereof. The preparation method comprises the following steps of: preparing a sol solution by taking 1,2-bi(triethoxy silicon substrate) ethane (BTEE) as a precursor and adding surfactant P123, HCl, ethanol and deionized water; and then obtaining the super-low k material thin film by adopting a spin coating technology and carrying out post annealing treatment. By virtue of the control on the proportions of the precursor, the surfactant, catalyst and solvent, as well as the control on spin coating film-forming conditions and post treatment conditions, the super-low k material SiCOH thin film, which has the characteristics that the k value is 2.1-2.5, the leakage current density under electric field intensity of 1MV/cm is 1.5*10<-6> to 3.4*10<-9> A/cm<2>, and the Young modulus is 21.05-24.15 Gpa, is obtained.

The invention provides a high-temperature heat treatment device under a magnetic field and a method thereof for preparing a bismuth ferrite film. The device comprises a tube type heating furnace, wherein the tube type heating furnace is arranged between magnet pole heads of a direct current water-cooling magnet, the direct current water-cooling magnet is connected with a direct-current magnet power supply and a circulating water-cooling system, the heating cavity of the tube type heating furnace is communicated with a vacuumizing system and an atmosphere control system; the tube type heating furnace is also connected with a temperature controller; the water-cooling cavity is formed by adopting a double-layer nonmagnetic stainless steel material by the shell of the tube type heating furnace; heating bodies are connected in series by four silicon carbide rods; a high-temperature resistant aluminum oxide heat insulating fiber material is used as a heat insulating material; and a high-temperature aluminum oxide ceramic tube or a quartz glass tube is used as a furnace tube. The device has the characteristics of small volume, high magnetic field utilization ratio and heating efficiency,and the like, can be used for carrying out the synthesis and the heat treatment on materials below 2 Tesla of the magnetic field and under the condition of vacuum or atmosphere. The microstructure and the properties of the bismuth ferrite film prepared by the device are improved.

The invention provides a multi-quantum well layer growing method of a micro LED. A multi-quantum well layer comprises a GaN barrier layer and an In<x>Ga<1-x>N well layer, wherein 0<X<1. Hydrogen is introduced in the process of forming the GaN barrier layer and hydrogen is not introduced in the process of forming the In<x>Ga<1-x>N well layer. According to the invention, by independently introducingthe hydrogen in the GaN barrier layer, the crystallization quality of the barrier layer is improved; stress between the GaN barrier layer and the In<x>Ga<1-x>N well layer; dislocation density is reduced; anti-static electricity ability and anti-electricity leakage performance of an epitaxial layer are improved; by further inserting a blocking layer between the GaN barrier layer and the In<x>Ga<1-x>N well layer, hydrogen possibly generated in the switching processes of growing the GaN barrier layer and the In<x>Ga<1-x>N well layer can be effectively prevented from overflowing to the In<x>Ga<1-x>N well layer to damage the In components; and the blocking layer is capable of allowing the In components to be quite uniformly distributed.

The invention provides a method for forming a semiconductor device, comprising the following steps: providing a substrate, a grid structure positioned on the substrate and a source area and a drain area which are both positioned in two side substrates of the grid structure; forming a nickel alloy layer on the exposed substrate surface containing nickel and at least one of other metals and having the thickness of 150-400 angstrom; and annealing the nickel alloy layer to form a nickel silicide in the substrate. According to the method, the diffusing capacity of the subsequently-formed nickel silicide in platinum is improved through improving the thickness of the nickel alloy layer which is in the range of 150-400 angstrom to enhance the diffusion barrier performance of the platinum element to the nickel element, thereby avoiding the diffusion of nickel to channel regions below a gate oxidation layer, reducing the generation of NiSi2 layers and improving the problem of deteriorating the electric leakage performance due to the development of the NiSi2 layer to channels.

The invention discloses a composite doped bismuth ferrite-barium titanate binary lead-free ferroelectric ceramic material, a preparation method and application thereof, belongs to the field of lead-free ferroelectric ceramic materials, particularly relates to the composite doped bismuth ferrite-barium titanate binary lead-free ferroelectric ceramic material, the preparation method and applicationthereof, and aims to solve the problem that the BFO ceramic prepared by the conventional solid phase synthesis method has poor ferroelectric performance and serious electric leakage. The chemical general formula of the ceramic material is (1-y)BiFeO<3-y>Ba<1-x>(Li<0.5><+>A<0.5><3+>)<x>TiO3. The ceramic material is obtained by adopting a sintering manner combining SPS rapid low-temperature sintering and solid phase synthesis, the system is a perovskite phase, and has no impurity phase, the prepared ceramic material has excellent electrical properties and relatively high Curie temperature, the preparation process of the material is stable, and the material has a relatively good application prospect. The prepared ceramic material is used as an electronic component in fields of temperature-stable capacitors and high-temperature applications.

The invention discloses a lateral high-voltage bipolar junction transistor and a manufacturing method thereof; comprising a P-type substrate, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, a P-type isolation penetration region, and an N-type penetration region , P-type body region, N-type heavily doped region, N-type heavily doped ring region, pre-oxidation layer, field oxygen layer, TEOS metal front dielectric layer, emitter metal, collector metal and base metal; the present invention is based on conventional On the basis of the transverse bipolar junction collective tube, an N-type annular injection is added between the collector and the emitter, and then by optimizing the layout of the first layer of metal, the metal is fully covered on the collector. beyond twice the junction depth of the collector region. Through simulation and actual tape-out results, it can be concluded that the horizontal high-voltage bipolar junction transistor of the present invention can increase BVcbo by more than 40%, increase BVceo by more than 30%, and increase the leakage capacity by an order of magnitude when other parameters have little influence. The invention provides a lateral high-voltage bipolar junction transistor.

The invention provides a silicon-controlled rectifier and a manufacturing method thereof. The silicon-controlled rectifier comprises a semiconductor substrate, a first N well, a P well, a second N well, first/second high-concentration P-type doping, first/second high-concentration N-type doping and third high-concentration P-type doping, wherein the first N well, the P well and the second N well are adjacent in sequence; the first/second high-concentration P-type doping and the first/second high-concentration N-type doping are located on the upper part of the first/second N well; the third high-concentration P-type doping is located at the upper part of the P well; a first/second grid electrode is arranged above the first/second N well between the first/second high-concentration N-type doping and the third high-concentration P-type doping; and the first/second high-concentration P-type doping, the first/second high-concentration N-type doping and the first/second grid electrode are connected to form a first/second device pole. Accordingly, the first/second device pole is connected with the input and output end of the positive/negative high voltage, PNPN channels without a conduction condition are formed, a bidirectional anti-static protection function suitable for the positive/negative high voltage at the same time is achieved in an applied circuit, and good electric leakage performance is achieved.

The invention provides a process method of a shielding gate trench type device. The process method comprises the steps of providing a substrate; forming a first trench on the substrate; sequentially forming a first oxide layer and a second oxide layer in the first trench, and obtaining a second trench, wherein the density of the first oxide layer is greater than that of the second oxide layer; forming a shielding gate in the second trench; forming a third oxide layer on the shielding gate, wherein the density of the third oxide layer is greater than that of the second oxide layer; and partially etching the first oxide layer, the second oxide layer and the third oxide layer to enable the thicknesses of the first oxide layer, the second oxide layer and the third oxide layer to be reduced, enabling the surface topography of the remaining second oxide layer and the remaining third oxide layer to be the same as the surface topography of the shielding gate, and enabling the thickness of thecombination formed by the remaining first oxide layer, the second oxide layer and the third oxide layer to be uniform, and thus improving the electric leakage performance between a control gate and the shielding gate.

A method and apparatus for managing a multi-port amplifier. In one illustrative embodiment, an apparatus comprises the multi-port amplifier and a controller. The multi-port amplifier is configured to amplify a plurality of signals to form a plurality of amplified signals. The controller is configured to send a plurality of control adjustments to a plurality of equalizers in the multi-port amplifier to improve leakage performance of the multi-port amplifier.

The invention relates to a dielectric film and a preparation method thereof. The preparation method comprises the steps: adopting an interface charge accumulation model of the first material and the second material and obtaining a thickness ratio of the first material and the second material and a leakage charge surface density of the interface between the first material and the second material; and preparing the dielectric film formed of the first material and the second material of the thickness ratio. Compared with the original film, the dielectric film effectively improves the leakage performance, reduces energy loss and improves breakdown electric field so as to improve the energy storage characteristics.

The invention provides a method for improving the surface roughness of a shielding gate. The method comprises the steps of providing a substrate, and forming a graphical hard mask on the substrate; taking the graphical hard mask as a mask, and etching the substrate to form a first trench; forming a gate dielectric layer in the first trench, and obtaining a second trench; filling the second trenchwith polycrystalline silicon, and covering the gate dielectric layer and the residual hard mask; executing a grinding process, and stopping grinding on the surface of the hard mask to flatten the surface of the polycrystalline silicon; performing dry etching on the polycrystalline silicon for the first time, and removing the polycrystalline silicon above the second trench; and carrying out seconddry etching on the polycrystalline silicon subjected to the first dry etching to form a shielding gate, wherein the surface of the shielding gate is flat. The problem that the surface of the formed shielding gate is rough can be solved, so that a process window of a dielectric layer formed between the shielding gate and the control gate is increased, and the electric leakage performance between the control gate and the shielding gate is improved.

The invention discloses an active switch, a manufacturing method thereof and a display panel. The active switch comprises a substrate, a buffer layer, an active layer, a gate insulation layer, a firstgate, a second gate, a passivation layer, a source electrode and a drain electrode which are stacked in sequence; the active layer is composed of indium gallium zinc oxide; the first gate and the second gate are arranged in parallel. and is located between the source electrode and the drain electrode; the source electrode and the drain electrode penetrate through the passivation layer and are connected with the two ends of the active layer respectively. With the active switch with the double-top-gate structure adopted, the parallel double top gates are equivalent to two cascaded active switches which are controlled by the same gate signal; with the double-top-gate structure adopted, the off-state leakage current can be obviously reduced without influencing on-state current, so that the gate control capability can be improved, the electric leakage effect of a TFT is improved, and the stability of the indium gallium zinc oxide type active layer is improved.

The invention discloses a fast wine brewing machine comprising a case; a case lid is arranged on the top of the case, and the case lid and the case are rotatingly connected through a hinge shaft. Theinterior of the case is a wine brewing chamber, and the wine brewing chamber is 70 cm in depth; a control panel is arranged on the front side face of the case and has a lip opening switch, a first heat generating pipe switch, a second heat generating pipe switch and a pot bottom switch; two heat generating pipes are arranged in the wine brewing chamber, one of the heat generating pipes has a powerof 6 kW, the other one of the heat generating pipes has a power of 3 kW, and the two heat generating pipes are connected with the first heat generating pipe switch and the second heat generating pipeswitch respectively. The first heat generating pipe switch is connected with a second switch indication lamp, and the second heat generating pipe switch is connected with a third switch indication lamp. The device has the advantages of rapid processing, high output, and mellow taste of produced wine, overall sealing, good electric discharge and leakage effects and the like.

The invention discloses a lateral high-voltage power bipolar junction transistor and a manufacturing method thereof; specifically, on the basis of a conventional lateral power bipolar junction collective transistor, a N-type annular implantation, and by optimizing the layout of all metals in the first layer, the first metal layer of the collector is completely covered on the collector area, and the size exceeds twice the junction depth of the collector area, while the emitter metal passes through hole and the second metal lead out. Theoretical analysis When the device is in the reverse withstand voltage working state, the edge of the collector junction is covered by the metal field plate, so that the curvature effect of the edge surface junction is greatly reduced when the depletion region diffuses, and the withstand voltage increases sharply, while the N-ring Adding can greatly reduce the leakage current between the collector and emitter of the device. Through the simulation and actual tape-out results, it can be concluded that the horizontal high-voltage power bipolar junction transistor of the present invention can increase BVcbo by more than 40%, BVceo by more than 40%, and the leakage capacity by an order of magnitude under the condition that other parameters have little influence.