Electrostatic protection structure of image sensor and image sensor

Abstract

The present invention provides an electrostatic protection structure of an image sensor and an image sensor, the image sensor comprises: a substrate including a plurality of pixel regions; a first metal interconnection layer arranged on one side of the substrate, including a pixel peripheral circuit; and a second metal layer arranged on the other side of the substrate. The electrostatic protectionstructure comprises: a first electrostatic discharge protection circuit arranged on the first metal interconnection layer and a second electrostatic discharge protection circuit arranged on the second metal layer; wherein the impedance of the second electrostatic discharge protection circuit is smaller than that of the first electrostatic discharge protection circuit, and the second electrostaticdischarge protection circuit and the first electrostatic discharge protection circuit have at least one access point. The electrostatic protection structure can reduce the resistance of a leakage path and improve the electrostatic discharge performance of a chip under the premise of not increasing the chip area.

Description

technical field [0001] The invention relates to the technical field of image sensors, in particular to an electrostatic protection structure of an image sensor and an image sensor. Background technique [0002] Back-illuminated (BSI) CMOS image sensors have many advantages over front-illuminated (FSI) CMOS image sensors, for example: the quantum efficiency of small-sized pixels can be greatly improved to adapt to the trend of high resolution; the thinning of the substrate makes the substrate The resistance is greatly increased, the propagation of noise in the substrate is suppressed, and the signal-to-noise ratio is improved. However, the increase in substrate resistance makes the chip's Electro-Static Discharge (ESD) performance more dependent on the ESD ring. To reduce the resistance of the ESD ring in a large-size chip requires a corresponding increase in the ESD ring. The width of the chip greatly increases the chip area and increases the manufacturing cost of the chip....

AI Technical Summary

Problems solved by technology

However, the increase in substrate resistance makes the chip's Electro-Static Discharge (ESD) performance more dependent on the ESD ring. To reduce the resistance of the ESD ring in a large-size chip requires a corresponding increase in the ESD ring. The width of the chip greatly increases the chip area and increases the manufacturing cost of the chip

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