Manufacturing method of array substrate, array substrate and display device

Abstract

The invention provides a manufacturing method of an array substrate, an array substrate and a display device. The manufacturing method of the array substrate includes the step of arranging a grid metal layer on the substrate and the step of arranging a source drain metal layer on the substrate, the grid metal layer comprises a grid electrode of a thin film transistor and a first pole plate of a storage capacitor, and the source drain metal layer comprises a source electrode and a drain electrode of the thin film transistor and a second pole plate of the storage capacitor; between the step of arranging the grid metal layer and the step of arranging the source drain metal layer, the manufacturing method of the array substrate further includes the steps that at least one non-channel contact interface grid insulating layer is arranged on the substrate, the part, corresponding to the grid electrode and / or the first pole plate, of the non-channel contact interface grid insulating layer is graphed and wholly or partially thinned; a channel contact interface grid insulating layer which is not graphed is arranged on the substrate, and a channel layer of the thin film transistor is arranged on the channel contact interface grid insulating layer. The electrical properties and the storage capacitance of the thin film transistor are improved, and stray capacitance is reduced.

Description

technical field [0001] The present invention relates to the technical field of manufacturing an array substrate, in particular to a method for manufacturing an array substrate, an array substrate and a display device. Background technique [0002] In the existing manufacturing process of the array substrate, the gate insulating layer is simultaneously the dielectric layer of the thin film transistor and the dielectric layer of the storage capacitor. When simply selecting a gate insulating material with a low dielectric constant or increasing the thickness of the gate insulating layer to reduce the parasitic capacitance to improve the response speed, the characteristics and storage capacitance of the thin film transistor will be reduced at the same time, resulting in insufficient charging of the thin film transistor on the array substrate. This then leads to problems with the image of the display device. Conversely, if the electrical characteristics and storage capacitance o...

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Problems solved by technology

When simply selecting a gate insulating material with a low dielectric constant or increasing the thickness of the gate insulating layer to reduce the parasitic capacitance to improve the response speed, the characteristics and storage capacitance of the thin film transistor will be reduced at the same time, resulting in insufficient charging of the thin film transistor on the array substrate. which in turn causes problems with the image on the display

Conversely, if the electrical characteristics and storage capacitance of thin film transistors are improved simply by using an ultra-thin gate insulating layer or increasing the dielectric constant of the gate insulating layer, it will also lead to an increase in parasitic capacitance, which will lead to leakage of the array substrate, life and reliability. Sexual variation and other issues

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