Super-low dielectric constant (k) material thin film and preparation method thereof

An ultra-low dielectric constant, material thin film technology, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as mechanical performance degradation, achieve smooth surface, good leakage performance and breakdown performance, and the effect of simple process

Inactive Publication Date: 2012-09-19
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, with the reduction of the k value of the interconnect dielectric material, its mechanical properties are also gradually degraded.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0026] In order to obtain ultra-low K material thin films, the following steps can be implemented:

[0027] (1) Will (EtO) 3 Si-CH 2 -CH 2 -Si(OEt) 3 ,P 123 , hydrochloric acid, ethanol and water were mixed, and then the above mixture was placed in an oil bath at 60° C. and stirred for 2 hours to obtain a film-forming liquid. The molar ratio of substances in the above mixture is: (EtO) 3 Si-CH 2 -CH 2 -Si(OEt) 3 :P 123 :HCl:H 2 O:EtOH=0.5:1.2×10 -2 : 1.8×10 -2 :20:13.9.

[0028] (2) Drop the film-forming solution prepared above onto the cleaned silicon wafer, and spin-coat to form a film after standing for 5 seconds. The rotational speed control in the spin-coating process was divided into three stages: 10 seconds at 800 rpm; 30 seconds at 3000 rpm; 10 seconds at 1000 rpm. The spin-coating process was completed at room temperature (25°C).

[0029] (3) The above film was placed in an oven and aged in an environment of 60° C. for 70 hours.

[0030] (4) Put the ag...

Embodiment 2

[0034] (1) Will (EtO) 3 Si-CH 2 -CH 2 -Si(OEt) 3 ,P 123, hydrochloric acid, ethanol and water were mixed, and then the above mixture was placed in an oil bath at 60° C. and stirred for 2 hours to obtain a film-forming liquid. The molar ratio of the above substances in the sample is: (EtO) 3 Si-CH 2 -CH 2 -Si(OEt) 3 :P 123 :HCl:H 2 O: EtOH=0.3: 1.2×10 -2 : 1.8×10 -2 :20:13.9.

[0035] (2) Drop the film-forming solution prepared above onto the cleaned silicon wafer, and spin-coat to form a film after standing for 5 seconds. The rotational speed control in the spin-coating process was divided into three stages: 10 seconds at 800 rpm; 30 seconds at 3000 rpm; 10 seconds at 1000 rpm. The spin-coating process was completed at room temperature (25°C).

[0036] (3) The above film was placed in an oven and aged in an environment of 60° C. for 70 hours.

[0037] (4) Put the aged film into an annealing furnace, blow nitrogen gas, slowly raise from room temperature to 350°C,...

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Abstract

The invention belongs to the technical field of super-large-scale integrated circuits and particularly relates to a super-low k material thin film and a preparation method thereof. The preparation method comprises the following steps of: preparing a sol solution by taking 1,2-bi(triethoxy silicon substrate) ethane (BTEE) as a precursor and adding surfactant P123, HCl, ethanol and deionized water; and then obtaining the super-low k material thin film by adopting a spin coating technology and carrying out post annealing treatment. By virtue of the control on the proportions of the precursor, the surfactant, catalyst and solvent, as well as the control on spin coating film-forming conditions and post treatment conditions, the super-low k material SiCOH thin film, which has the characteristics that the k value is 2.1-2.5, the leakage current density under electric field intensity of 1MV/cm is 1.5*10<-6> to 3.4*10<-9> A/cm<2>, and the Young modulus is 21.05-24.15 Gpa, is obtained.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuits, and in particular relates to an ultra-low-k material thin film and a preparation method thereof. Background technique [0002] Since the scale of the integrated circuit is continuously expanding, the feature size is also reduced, which leads to a sharp increase of the RC delay of the interconnection of the integrated circuit, thereby restricting the improvement of the performance of the integrated circuit. In order to reduce the RC delay, it is necessary to use low-resistivity copper wires to replace traditional aluminum wires, and to use low dielectric constant (low-k) interconnection media instead of commonly used SiO 2 Medium (k ≈ 3.9). According to the International Technology Roadmap for Semiconductors (ITRS) [1] , when the integrated circuit enters the technology node of 45 / 32nm, the k value of the interconnection medium should be between 2.0 and 2.6. In ord...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/532
Inventor 丁士进孟庆伟蒋涛张卫
Owner FUDAN UNIV
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