Transverse high-voltage power bipolar junction transistor and manufacturing method thereof
A bipolar junction, lateral high-voltage technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of insufficient withstand voltage and large leakage of lateral high-voltage power bipolar junction transistors, and achieve curvature Effect reduction, leakage capacity improvement, and the effect of reducing leakage current
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0069] like figure 1 and figure 2 As shown, a lateral high-voltage power bipolar junction transistor is characterized in that it includes a P-type substrate 100, an N-type buried layer 101, a P-type buried layer 102, an N-type epitaxial layer 103, and an N-type heavily doped ring region. 104, P-type isolation penetration region 105, N-type penetration region 106, P-type collector region 107, N-type heavily doped base region 108, P-type emitter region 109, pre-oxidation layer 110, field oxygen layer 111, TEOS metal Front dielectric layer 112, collector first layer metal 113, emitter first layer metal 114, base first layer metal 115, emitter second layer metal 116, collector second layer metal 117, base second layer Metal 118 and IMD planarization dielectric 119 .
[0070] The N-type buried layer 101 is located in the middle of the upper surface of the P-type substrate 100 .
[0071] The P-type buried layer 102 is located at both ends of the upper surface of the P-type subst...
Embodiment 2
[0090] like Figure 3 ~ Figure 13 As shown, a method for manufacturing a lateral high-voltage power bipolar junction transistor is characterized in that it comprises the following steps:
[0091] 1) Select a NTD single chip with less defects, with a thickness of about 500-700 μm and a resistivity of 5-30Ω·cm, marking, cleaning, and drying for later use;
[0092] 2) Growth of a thick oxide layer Temperature 1100~1150℃, time 100min~120min, dry humidification oxidation conditions.
[0093] 3) One photolithography, after photolithography etch to remove glue, grow a thin oxide layer Temperature 1000~1020℃, time 30min~40min, pure dry oxidation conditions.
[0094] The N-type buried layer 101 is implanted in the middle of the wafer substrate, and the ion implantation conditions are: dose 1e15-5e15cm -2 , Energy 40 ~ 80KeV.
[0095] The redistribution conditions are: aerobic conditions 1000 ° C, the thickness of the oxide layer is Reannealing temperature pure N 2 , 1100~1150...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com