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High-voltage substrate PNP bipolar junction type transistor and manufacturing method thereof

A technology of bipolar junction type and manufacturing method, which is applied in the direction of transistor, semiconductor/solid-state device manufacturing, semiconductor device, etc., can solve the difficulties, the parameters such as withstand voltage and gain, frequency, and device size of bipolar junction devices are difficult to reconcile, etc. problem, to achieve the effect of simple and feasible structure

Inactive Publication Date: 2018-08-17
CHONGQING ZHONGKE YUXIN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For a single active component in a bipolar process, the designer hopes that the characteristics of the device are optimal in all aspects. The bipolar junction transistor has a series of advantages such as high gain, high current, and high frequency, but as With the continuous development of bipolar process integration technology, the disadvantages displayed are becoming more and more obvious, especially in the high-voltage field. The withstand voltage and gain, frequency, device size and other parameters of bipolar junction devices are quite difficult to reconcile. Therefore, comprehensive Considering the various factors becomes a very difficult problem for the designer

Method used

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  • High-voltage substrate PNP bipolar junction type transistor and manufacturing method thereof
  • High-voltage substrate PNP bipolar junction type transistor and manufacturing method thereof
  • High-voltage substrate PNP bipolar junction type transistor and manufacturing method thereof

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Embodiment 1

[0053] Such as figure 1 with figure 2 As shown, a high-voltage substrate PNP bipolar junction transistor is characterized in that it includes: a P-type substrate 101, a P-type buried layer 102, an N-type epitaxial layer 103, a P-type isolation penetration region 104, and a field oxygen layer 105, pre-oxidation layer 106, P-type emitter / collector region 107, N-type heavily doped base region 108, TEOS metal front dielectric layer 109, first layer metal 110 in collector region, first layer metal 111 in emitter region and Base first layer metal 112 .

[0054] The P-type buried layer 102 covers both ends of the upper surface of the P-type substrate 101 .

[0055] The N-type epitaxial layer 103 covers part of the surface on the P-type substrate 101 . The N-type epitaxial layer 103 is in contact with the P-type buried layer 102 .

[0056] The P-type isolation penetration region 104 covers the P-type buried layer 102 . The P-type isolation penetration region 104 is in contact with...

Embodiment 2

[0070] Such as Figure 3 to Figure 9 Shown, a kind of manufacturing method of high voltage substrate PNP bipolar junction transistor is characterized in that, comprises the following steps:

[0071] 1) Select a NTD single chip with less defects, with a thickness of about 500-700 μm and a resistivity of 5-30Ω·cm, marking, cleaning, and drying for later use;

[0072] 2) Growth of a thick oxide layer Temperature 1100~1150℃, time 100min~120min, dry humidification oxidation conditions.

[0073] 3) One photolithography, after photolithography etch to remove glue, grow a thin oxide layer Temperature 1000~1020℃, time 30min~40min, pure dry oxidation conditions.

[0074] Implant the P-type buried layer 102 at both ends of the wafer substrate, and the ion implantation conditions are: dose 4e15-8e15cm -2 , Energy 60 ~ 100KeV.

[0075] The redistribution condition is: pure N 2 Atmospheric annealing temperature, 1100-1150°C, time 100min-120min. Remove the oxide layer.

[0076] 4) ...

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Abstract

The invention discloses a high-voltage substrate PNP bipolar junction type transistor and a manufacturing method thereof. Specifically, on the basis of a conventional substrate PNP bipolar junction type transistor, first layer of metal is added to a collector region edge on one side tightly attached to base, and the first layer metal edge of a collector covers the collector region, wherein the dimension exceeds 1-5 times of junction depth of the collector region; the first layer metal edge of an emitter also covers an emitter region, wherein the dimension exceeds 1-5 times of junction depth ofthe emitter region; according to theoretical analysis when a device is in a reversed CE / EB / CB withstand voltage working state, the withstand voltage junction edge is covered with a metal field plate,so that the curvature effect of an edge hook face structure in depletion region diffusion is greatly lowered, and BV<cbo> / BV<ceo> / BV<ebo> withstand voltage is sharply increased, while forward gain has no any loss; and therefore, the problem in compromise and realization of gain and withstand voltage in the substrate PNP transistor is well solved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing process, in particular to a high-voltage substrate PNP bipolar junction transistor and a manufacturing method thereof. Background technique [0002] In the mid-1940s, due to the increasingly complex electronic device systems such as navigation, communication, and weaponry, the demand for integration and miniaturization of electronic circuits became increasingly urgent. In 1959, Fairchild Semiconductor Corporation of the United States finally gathered the technological achievements of its predecessors The first practical silicon integrated circuit was manufactured by using planar bipolar process integration technology, which created a precedent for the application and vigorous development of integrated circuits. Most widely, with the continuous advancement of integrated circuit technology, despite the huge challenge of CMOS technology, bipolar technology still develops still by virtue o...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/10H01L21/336H01L29/73
CPCH01L29/0603H01L29/1004H01L29/66234H01L29/73
Inventor 刘建刘青税国华张剑乔陈文锁张培健
Owner CHONGQING ZHONGKE YUXIN ELECTRONICS
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