Transverse high-voltage bipolar junction transistor and manufacturing method thereof
A bipolar junction, lateral high-voltage technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as large leakage and insufficient withstand voltage of lateral high-voltage bipolar junction transistors, and achieve the curvature effect. The effect of reducing and reducing leakage current
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Embodiment 1
[0059] Such as figure 1 and figure 2 As shown, a lateral high-voltage bipolar junction transistor is characterized in that it includes a P-type substrate 100, an N-type buried layer 101, a P-type buried layer 102, an N-type epitaxial layer 103, and an N-type heavily doped ring region 104. , P-type isolation penetration region 105, N-type penetration region 106, P-type annular body region 107, N-type heavily doped region 108, field oxygen layer 109, pre-oxidation layer 110, TEOS metal pre-dielectric layer 111, emission region metal 112 , collector metal 113 and base metal 114 .
[0060] The N-type buried layer 101 is located at the center of the upper surface of the P-type substrate 100 .
[0061] The P-type buried layer 102 is located at both ends of the upper surface of the P-type substrate 100 .
[0062] The N-type epitaxial layer 103 is located on the N-type buried layer 101 , and the N-type epitaxial layer 103 is in contact with the P-type substrate 100 , the N-type bu...
Embodiment 2
[0075] Such as Figure 3 ~ Figure 11 As shown, a method for manufacturing a lateral high-voltage bipolar junction transistor is characterized in that it comprises the following steps:
[0076] 1) Select a NTD single chip with less defects, with a thickness of about 500-700 μm and a resistivity of 5-30Ω·cm, marking, cleaning, and drying for later use;
[0077] 2) Growth of a thick oxide layer Temperature 1100~1150℃, time 100min~120min, dry humidification oxidation conditions.
[0078] 3) One photolithography, after photolithography etch to remove glue, grow a thin oxide layer Temperature 1000~1020℃, time 30min~40min, pure dry oxidation conditions.
[0079] The N-type buried layer 101 is implanted in the middle of the wafer substrate, and the ion implantation conditions are: dose 1e15-5e15cm -2 , Energy 40 ~ 80KeV.
[0080] The redistribution conditions are: aerobic conditions 1000 ° C, the thickness of the oxide layer is The re-annealing temperature is pure N2, 1100-11...
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