Porous ultra-low dielectric constant material film and preparation method thereof

A low dielectric constant, material thin film technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problem of not meeting the requirements of k value, and achieve ultra-low dielectric constant, good controllability, and simple process. Effect
CN101789418AInactive Publication Date: 2010-07-28FUDAN UNIV

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
FUDAN UNIV
Publication Date
2010-07-28
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention belongs to the technical field of integrated circuit manufacture, in particular to a porous ultra-low dielectric constant material film and a preparation method thereof. The preparation procedures of the invention are as follows: using the sol-gel process, taking organo-siloxane as a precursor, and preparing the porous ultra-low dielectric constant material by controlling the ratio of the precursor to a pore forming agent, a catalyst and a solvent, the solution concentration, and the synthesis, post-treatment and annealing temperatures and the like. The process has simple procedures, and the prepared film has ordered nano-pores, even surface, low roughness and good thermal stability, the dielectric constant is 1.9-2.0, and the leakage current density is from10-8 to10-9A / cm<2>order of magnitude at 1MV / cm.
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Description

technical field

[0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to an ultra-low dielectric constant porous material film and a preparation method thereof. Background technique

[0002] With the development of integrated circuit technology, chips with high speed, high device density, low power consumption and low cost have increasingly become the main products of VLSI manufacturing. At this time, the density of wires in the chip continues to increase, the width and spacing of wires continue to decrease, and the parasitic effects generated by the resistance (R) and capacitance (C) in the interconnect become more and more obvious. Replace traditional SiO with low dielectric constant film 2 (k ~ 4.0) can not only reduce RC delay, but also reduce power consumption and signal crosstalk. At present, there are two main ways to reduce the k value of materials: one is to reduce the density of materials, and the other is to reduc...

Claims

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