Formation method of transistor

A technology of transistors and semiconductors, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as transistor performance needs to be improved

Inactive Publication Date: 2016-10-19
SEMICON MFG INT (SHANGHAI) CORP
View PDF4 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The performance of transistors formed by

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Formation method of transistor
  • Formation method of transistor
  • Formation method of transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] The performance of the conventionally formed transistors still needs to be improved, for example, the problem of the short channel effect still exists in the transistors formed by the prior art.

[0035] Research has found that in the prior art, there are problems of uneven ion concentration distribution and inaccurate position in the pocket implant region formed by ion implantation in the pocket implant region, especially in the parts near the bottom of the gate electrode and the channel region of the transistor. It is outstanding that the transistor still has the problem of short channel when it is working. Further studies have found that the reason for the uneven distribution of ion concentration and inaccurate positions in the pocket implantation region is that during the pocket ion implantation process, the gate electrode and offset sidewalls will affect the implanted ion beam.

[0036]To this end, the present invention provides a method for forming a transistor. A...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Widthaaaaaaaaaa
Login to view more

Abstract

A method for forming a transistor, comprising: providing a semiconductor substrate, forming a gate dielectric layer and a gate electrode on the gate dielectric layer on the semiconductor substrate, and the gate electrode includes a first gate electrode on the gate dielectric layer layer and a second gate layer located on the first gate layer, the material of the first gate layer is different from the material of the second gate layer; a part of the width is etched along the sidewall of the first gate layer Openings are formed on both sides of the remaining first gate layer at the bottom of the second gate layer; after the openings are formed, the first ion implantation is performed using the gate electrode as a mask, and on both sides of the gate electrode A lightly doped region is formed in the semiconductor substrate; after the opening is formed, the gate electrode is used as a mask to perform an angled second ion implantation, and a pocket-shaped implanted region is formed in the semiconductor substrate at the bottom of the gate electrode. The pocket-shaped implanted region The doping type of the region is opposite to that of the shallowly doped region. The transistor formed by the method of the invention can better prevent the generation of short channel effect.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] With the continuous improvement of the integration of semiconductor devices, the feature size is gradually reduced, the length of the channel of the MOS transistor is also gradually reduced, and the thickness of the gate dielectric layer is also continuously reduced. Since the gate voltage will not continue to decrease (currently at least 1V), so that the electric field strength received by the gate oxide layer becomes larger, time-dependent dielectric breakdown (time dependent dielectric breakdown, TDDB) is also more likely to occur, and it is easy to form a hot carrier injection effect (Hot Carrier Injection, HCI). In the prior art, LDD (Lightly Doped Drain, Lightly Doped Drain Implantation) ion implantation is usually used to optimize the hot carrier injection effect. [0003] However, the above metho...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/336
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products