Formation method of transistor

A technology of transistors and semiconductors, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as transistor performance needs to be improved
CN106033730AInactive Publication Date: 2016-10-19SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN ยท China
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2016-10-19
Estimated Expiration
Not applicable ยท inactive patent

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Abstract

A method for forming a transistor, comprising: providing a semiconductor substrate, forming a gate dielectric layer and a gate electrode on the gate dielectric layer on the semiconductor substrate, and the gate electrode includes a first gate electrode on the gate dielectric layer layer and a second gate layer located on the first gate layer, the material of the first gate layer is different from the material of the second gate layer; a part of the width is etched along the sidewall of the first gate layer Openings are formed on both sides of the remaining first gate layer at the bottom of the second gate layer; after the openings are formed, the first ion implantation is performed using the gate electrode as a mask, and on both sides of the gate electrode A lightly doped region is formed in the semiconductor substrate; after the opening is formed, the gate electrode is used as a mask to perform an angled second ion implantation, and a pocket-shaped implanted region is formed in the semiconductor substrate at the bottom of the gate electrode. The pocket-shaped implanted region The doping type of the region is opposite to that of the shallowly doped region. The transistor formed by the method of the invention can better prevent the generation of short channel effect.
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Description

technical field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique

[0002] With the continuous improvement of the integration of semiconductor devices, the feature size is gradually reduced, the length of the channel of the MOS transistor is also gradually reduced, and the thickness of the gate dielectric layer is also continuously reduced. Since the gate voltage will not continue to decrease (currently at least 1V), so that the electric field strength received by the gate oxide layer becomes larger, time-dependent dielectric breakdown (time dependent dielectric breakdown, TDDB) is also more likely to occur, and it is easy to form a hot carrier injection effect (Hot Carrier Injection, HCI). In the prior art, LDD (Lightly Doped Drain, Lightly Doped Drain Implantation) ion implantation is usually used to optimize the hot carrier injection effect.

[0003] However, the above metho...

Claims

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