4results about How to "Avoid short channel effects" patented technology

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a first transistor and a substrate; the buffer layer is positioned on one side of the substrate; the first metal layer is located on the side, away from the substrate, of the buffer layer, the first metal layer comprises a first grid electrode of the first transistor, the first grid electrode comprises a first surface, a convex body extending in the direction away from the substrate is formed on the first surface, the convex body has a first orthographic projection on the substrate, and the first surface located outside the convex body has a second orthographic projection on the substrate; the active layer is located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the orthographic projection of the first part of the active structure on the substrate at least partially covers the first orthographic projection; and a second metal layer comprising a first pole of the first transistor, the first pole of the first transistor comprising a second surface facing the substrate, the second surface being in contact with the second portion.

The application provides an insulated gate bipolar transistor and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor layer comprising a substrate, a cell region, a transition region and a terminal region; performing ion implantation of a second conductive type in the cell region to form a first body region; forming a plurality of interval arranged groove structures in the cell region; forming a shielding layer on the upper surface of the semiconductor layer to expose the cell region, and forming an emitter region and a second body region based on the shielding layer, the bottom surface of the second body region is below the first body region, the upper surface of the second body region is in the first body region, the first body region and the second body region form a body region, and rapid annealing is performed on the second body region and the emitter region. The body region is formed by twice ion implantation of low energy and high energy, so that the concentration peak of the doping particles is located in the body region, the threshold voltage consistency of the device is ensured, rapid annealing is performed on the second body region and the emitter region, and the influence of thermal stress on the device is reduced.

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a substrate; the spacing layer is located on one side of the substrate, the spacing layer comprises a first surface deviating from the substrate, at least one groove sunken towards the substrate is formed in the first surface, and the groove has a first orthographic projection on the substrate; the first metal layer is located on the first surface and comprises a first grid electrode of a first transistor; the active layer is insulated from the first metal layer and located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the active structure comprises a first part and a second part; the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection; the second metal layer is located on the side, away from the substrate, of the active layer, the second metal layer comprises a first electrode of the first transistor, the first electrode of the first transistor comprises a second surface facing the substrate, and the second surface makes contact with the second part.

The application belongs to the technical field of microelectronic process, and particularly relates to a preparation method of a self-aligned top gate field effect transistor based on two-dimensional material. The preparation method comprises the following steps: preparation of single-layer or multi-layer two-dimensional semiconductor material on a silicon / silicon dioxide or sapphire substrate, growth of an oxide dielectric layer, deposition of a top gate metal electrode on the oxide dielectric layer, selective etching of the oxide dielectric layer, and self-aligned deposition of a source-drain metal electrode in contact with the edge of the two-dimensional material. The metal material of the source-drain electrode is self-aligned deposited by using the microstructure formed by selective etching as a hard mask, and compared with a non-self-aligned process, the preparation method omits the step of source-drain patterning overlay, avoids the alignment deviation problem caused by size reduction, and is easier to prepare a short channel field effect transistor, so that the preparation method has a wide application prospect in advanced processes with continuously shrinking size.