8results about How to "Improve channel mobility" patented technology

The invention relates to a process method for improving channel mobility and gate dielectric layer reliability of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The process method comprises the following steps of: forming a channel layer on an epitaxial layer by adopting ion implantation; carrying out surface treatment on the SiC epitaxial layer in a sacrificial oxidation mode; forming SiO2 on the surface of SiC by adopting a low-pressure chemical vapor deposition process to serve as a gate dielectric layer; and performing an NO post-deposition annealing process on the gate dielectric layer. The SiC / SiO2 interface roughness formed by the method is reduced, the problem that carbon clusters and carbon particles are generated in traditional thermal oxidation is avoided, and the interface state density is reduced, so that the channel carrier mobility is enhanced; besides, a step-by-step low-pressure chemical vapor deposition process is adopted, gate dielectric layer densification is carried out in a gap between two or more stages of deposition processes, residues of a precursor in deposition are fully decomposed, stress of the gate dielectric layer is released, the electric leakage level of the gate dielectric layer is reduced, the reliability of the gate dielectric layer is enhanced, and the device yield is improved.

This disclosure provides a junction field-effect transistor (JFET) device, its fabrication method, and an electronic device. The p-type gate region is formed by implantation ions on the side of the n-drift layer away from the n+ substrate. Therefore, it eliminates the need for high-energy p-type ion deep implantation to achieve the p-type gate region, thereby improving production efficiency. The n-type channel layer can be formed using homoepitaxial growth, which improves device design flexibility and channel mobility. Therefore, compared to Figure 1, this disclosure avoids using deep p-type ion implantation to form the bottom p-type gate region and deep n-type ion implantation to form the n-type channel layer, thus improving device design flexibility, production efficiency, and channel mobility.

The present invention discloses a nanosheet transistor with a heterogeneous gate dielectric and a preparation method thereof; the nanosheet transistor comprises: a substrate, a source region, a drain region, a gate material and a plurality of nanosheet channel layers; wherein the gate material covers the nanosheet channel layer to form a gate structure; the source region, the gate structure and the drain region are sequentially arranged on the substrate along the channel direction; the channel direction is the direction from the source region to the drain region; a heterogeneous gate dielectric layer is arranged between the adjacent surfaces of the gate material and the nanosheet channel layer and between the adjacent surfaces of the gate material and the substrate; the heterogeneous gate dielectric layer comprises a plurality of gate dielectric materials continuously arranged along the channel direction, and the relative dielectric constants of the plurality of gate dielectric materials gradually decrease with the channel direction; the source region is isolated from the gate region by a first isolation dielectric; the drain region is isolated from the gate region by a first isolation dielectric. The present invention reduces the short channel effect of a small-sized field effect transistor, reduces the off-state current leakage, and improves the electrical performance of a small-sized semiconductor device.

This application discloses a SiC MOSFET, a SiC MOSFET preparation method, and an integrated circuit. In the SiC MOSFET, a gate electrode is located on two sides of a fin-shaped channel layer. Disposing the gate electrode on the two sides of the fin-shaped channel layer is conducive to reducing a width of the fin-shaped channel layer. This is favorable for global inversion of the fin-shaped channel layer, thereby forming a large carrier path in the fin-shaped channel layer. In this way, most carriers in the SiC MOSFET flow through an electron path formed in the fin-shaped channel layer, so that a quantity of carriers that flow on an edge of a gate oxide layer is reduced, thereby greatly improving channel mobility and also improving reliability of the gate oxide layer.

The present application relates to a kind of trench forming method and device with one side of sidewall inclined.The method comprises: preparing the required trench in the SiC substrate;The trench protection mask is filled in the above-mentioned trench, and the trench protection mask on the front main surface of SiC substrate is selectively masked and etched to obtain the inclined sidewall etching window located at one outer side of trench;The above-mentioned SiC substrate is inclined and placed on the inclined body, and the front main surface of SiC substrate is dry etched using inclined sidewall etching window to obtain the inclined sidewall formed by the trench after etching, and the trench protection mask is removed, wherein, after removing the trench protection mask, the sidewall of the trench protected by the trench protection film is vertical surface, and the other sidewall of the trench is the inclined sidewall.The present application can effectively prepare the trench with one side of sidewall inclined on SiC substrate, improve the channel mobility of SiC device, and is compatible with existing process.

The invention relates to an epitaxial structure for an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a preparation method and application thereof, in particular to the field of power devices, and the epitaxial structure comprises a buffer layer, a first drift layer, a second drift layer, an AlN layer, a first NO-doped 3C-SiC layer, an O-doped 3C-SiC layer and a second NO-doped 3C-SiC layer which are sequentially arranged on a substrate. According to the epitaxial structure provided by the invention, the epitaxial structure is designed, and the specific design of the first NO-doped 3C-SiC layer, the O-doped 3C-SiC layer and the second NO-doped 3C-SiC layer is adopted, so that the defects of low channel mobility and over-low threshold voltage caused by poor SiO2 / SiC interface quality and high interface state are overcome; therefore, the obtained power device has excellent channel mobility and reasonable threshold voltage.

The invention relates to a fin-structured metal-oxide field effect transistor and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the fin-structured metal-oxide field effect transistor comprises an n-type first semiconductor layer, an n-type second semiconductor layer, an n-type third semiconductor layer, a p-type fourth semiconductor region, an n-type fifth semiconductor region and a p-type sixth semiconductor region; a gate trench is etched on the n-type third semiconductor layer, a gate oxide layer is arranged in the gate trench and on the upper surface of the n-type third semiconductor layer, and a polycrystalline silicon gate is formed on the upper part of the gate oxide layer; oxide is deposited on the upper surface of the n-type third semiconductor layer to form a metal layer medium, Schottky contact and ohmic contact are formed on the metal layer medium, and the Schottky contact and the ohmic contact are not communicated with each other; the invention also comprises a first metallization layer and a second metallization layer. According to the invention, the on resistance of the device can be greatly reduced, the Schottky diode is embedded on the basis of not increasing the size of the device, and the bipolar degradation effect is avoided.

The application provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method, and the device structure comprises an N+ substrate, an N- epitaxial layer, an N+ buffer layer, a P-type well region, an N+ source region, a P+ shielding region, a polysilicon gate, a source metal and a drain metal. The application is based on an asymmetric trench gate silicon carbide MOSFET device, which has a channel on one side of a silicon carbide trench and is wrapped by P+ on the other side. The integrated FinFET structure increases the channel density, and at the same time, the extremely narrow Fin-shaped mesa reduces the electric field intensity at the channel and the interface scattering, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P+ structure wrapping the gate trench reduces the gate oxide electric field at the trench corner, so that the gate oxide electric field intensity of the device after the introduction of the FinFET structure is in the safe working range.