234results about How to "Reduce interface state density" patented technology

A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 Å. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.

A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 4.7×10²⁰ cm⁻³. The interface provides a channel surface having a (000-1)-orientation surface.

The invention discloses a light trapping structure for a thin film silicon/crystalline silicon heterojunction solar battery, which comprises a crystalline silicon substrate (2), a doped thin film silicon layer (3) on the crystalline silicon substrate (2), a transparent conductive electrode (4) on the doped thin film silicon layer (3), and a metal nano-structure (1) between the doped thin film silicon layer (3) and the transparent conductive electrode (4), a metal nano-structure (1) above the transparent conductive electrode (4), or a metal nano-structure (1) inside the transparent conductive electrode (4). The connecting surface of the crystalline silicon substrate (2) and the crystalline silicon substrate (2) is not specially woven with velvet. The light trapping structure acquires a light trapping effect by using a surface plasmon effect of the metal nano-structure.

A novel technique to quench electrical defects in CVD Al₂O₃ layers is disclosed. A small amount of silicon dopant to the aluminum oxide film reduces the leakage current as well as the gap interface trap density at the dielectric/silicon interface. The implanted silicon gives a better interface and improves the leakage characteristics of the dielectric.

The invention discloses a surface interface passivation layer of a high-efficiency crystalline silicon solar cell and a passivation method thereof, belonging to the technical field of solar energy manufacturing. An n +-type doping layer is arranged on the front surface of the p-type crystal silicon battery, and the surface of the n +-type doping layer and the surface of the p-type layer on the back surface of the p-type silicon substrate are passivated respectively. Plasma enhanced chemical vapor deposition (PECVD) technique was used to prepare four-layer passivation film on the n + layer of P-type silicon substrate. Plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) were used to prepare a four-layer passivation film on the p-type layer on the back surfaceof P-type silicon substrate, The structure order of the laminated passivation layer prepared by the patent of the invention has a vital effect on the passivation effect, and the laminated layers havemutual synergistic effect, and after passivation, the laminated passivation layer has excellent anti-reflection effect and good passivation effect, and the laminated passivation layer has excellent application prospect in p-type PERC batteries.

The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO₂) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.

An embodiment of a III-nitride semiconductor device and method for making the same may include a low resistive passivation layer that permits the formation of device contacts without damage to the III-nitride material during high temperature processing. The passivation layer may be used to passivate the entire device. The passivation layer may also be provided in between contacts and active layers of the device to provide a low resistive path for current conduction. The passivation process may be used with any type of device, including FETs, rectifiers, schottky diodes and so forth, to improve breakdown voltage and prevent field crowding effects near contact junctions. The passivation layer may be activated with a low temperature anneal that does not impact the III-nitride device regarding outdiffusion.

Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

A nitrided oxide layer on a silicon carbide layer is processed by annealing the nitrided oxide layer in a substantially oxygen-free nitrogen containing ambient. The anneal may be carried out at a temperature of greater than about 900° C., for example, a temperature of about 1100° C., a temperature of about 1200° C. or a temperature of about 1300° C. Annealing the nitrided oxide layer may be carried out at a pressure of less than about 1 atmosphere, for example, at a pressure of from about 0.01 to about 1 atm or, in particular, at a pressure of about 0.2 atm. The nitrided oxide layer may be an oxide layer that is grown in a N₂O and/or NO containing ambient, that is annealed in a N₂O and/or NO containing ambient or that is grown and annealed in a N₂O and/or NO containing ambient.

The invention provides a solar cell. The solar cell comprises a silicon wafer, a passivated tunnel layer and a doping thin film silicon layer, wherein passivated tunnel layer is arranged between the silicon wafer and the doping thin film silicon layer, the passivated tunnel layer is one of a silicon oxide/silicon oxynitride gradient lamination layer, a silicon oxynitride/silicon nitride gradient lamination layer and a silicon oxide/silicon oxynitride/silicon nitride gradient lamination layer, the silicon oxynitride is nitrogen doping silicon oxide or oxygen doping silicon nitride, and the nitrogen concentration of the silicon oxide/silicon oxynitride gradient lamination layer, the silicon oxynitride/silicon nitride gradient lamination layer and the silicon oxide/silicon oxynitride/silicon nitride gradient lamination layer is gradiently reduced from a part far away from a silicon wafer side to the silicon wafer side. Since the tunnel barriers of silicon nitride and silicon oxynitride are relatively low, the thickness of the passivated tunnel layer can be appropriately widened on the premise of ensuring the tunnel efficiency, thus, the holes of the passivated tunnel layer are favorably reduced, the generation and combination rate of current leakage are reduced, the process window is expanded, and the process stability is improved.

The invention relates to a method for preparing a direct current (DC) magnetron sputtering AZO/SiO2/p-SiSIS heterojunction photoelectric device, and belongs to the technical field of methods for preparing silicon-based heterojunction photoelectric devices. By growth of an ultrathin SiO2 layer through low-temperature thermal oxidation, DC magnetron sputtering of an AZO emitter, antireflection and collection of an electrode film, a novel AZO/SiO2/p-SiSIS ultraviolet-visible-near-infrared broad-spectrum heterojunction photoelectric device is successfully prepared. An I/V curve of the prepared AZO/SiO2/p-SiSIS heterojunction has good rectification characterisitic and very low reverse dark current, so a good heterojunction diode is formed between AZO and p-Si. Under the condition of AM 1.5 illumination, the open-circuit voltage VOC is 230mV, the photoelectric conversion efficiency eta is 0.025 percent, and the photovoltaic effect is obvious. By combining different characteristics of a wide band gap of the AZO and a relatively narrow band gap of a Si material for mutual complementation, the SIS heterojunction can be developed into a low-cost solar cell, and also can become an excellent-performance ultraviolet-visible-near-infrared enhanced broad-spectrum photoelectric detector.

A method for manufacturing a semiconductor device, comprises providing a semiconductor layer deposited on a substrate with heat treatment by using a flame of a gas burner fueled by a hydrogen-and-oxygen mixed gas as a heat source.

An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO₂/Si₃N₄ gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si₃N₄ portion of the SiO₂/Si₃N₄ gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO₂ portion of the SiO₂/Si₃N₄ gate insulation layer significantly reduces the leakage current.

The invention discloses a novel composite structure full back-side heterojunction solar cell and a preparation method thereof. The solar cell comprises an N-type silicon substrate, a silicon nitride film, an aluminum oxide film, intrinsic polycrystalline silicon, P-type polycrystalline silicon, and N-type polycrystalline silicon. The front surface of the N-type silicon substrate is coated with thealuminum oxide film. The aluminum oxide film is coated with the silicon nitride film. The intrinsic polycrystalline silicon, the P-type polycrystalline silicon, and the N-type polycrystalline siliconare deposited on the back surface of the N-type silicon substrate. The polycrystalline silicon layers are deposited by using horizontally placed silicon wafer LPCVD or horizontally placed silicon wafer PECVD, a homojunction layer can reduce an interface defect state and reduce interface recombination. A laser doping technology is used to realize the P-type polycrystalline silicon layer doping, ensure the service lives of minority carriers of the silicon substrate to the utmost extent and reduce the recombination current density of the contact of metal and silicon. In addition, the cell piecesof the cell with IBC structure fully utilize a solar spectrum to increase the short-circuit current density of the cell to the utmost extent.