15results about How to "Reduce interface state density" patented technology

The application provides a TOPCon cell and a preparation method thereof and a photovoltaic system, and relates to the field of solar cells. The TOPCon cell comprises a P-type silicon-based substrate and an N+ layer. The surface of the P-type silicon-based substrate extends in a direction away from the P-type silicon-based substrate and comprises, in sequence from the P-type silicon-based substrate, an N+ emitter layer, a silicon oxide layer, a first aluminum oxide layer, and a second aluminum oxide layer. The first aluminum oxide layer comprises a boron-doped aluminum oxide layer, and the second aluminum oxide layer comprises a phosphorus-doped aluminum oxide layer. The TOPCon cell adopts a double-layer gradient-doped aluminum oxide structure. The first aluminum oxide layer close to the P-type silicon-based substrate is a nanocrystalline aluminum oxide doped with boron, the B-O bond is used to enhance the interface chemical passivation, and the density of silicon dangling bonds is reduced. The second aluminum oxide layer close to the N+ emitter layer is an amorphous aluminum oxide doped with phosphorus. The phosphorus doping concentration gradient decreases, the electric field distribution can be controlled by P doping, and the hole recombination is inhibited.

The invention provides a high-k gate dielectric composite material, a preparation method thereof and a beta-Ga2O3 MOS (Metal Oxide Semiconductor) power device. The composite material comprises a beta-Ga2O3 substrate; the SiO2 interface buffer layer is formed on at least one surface of the beta-Ga2O3 substrate; the Al2O3 transition layer is formed on the surface of the SiO2 interface buffer layer; the AlON interface layer is formed on the surface of the Al2O3 transition layer; and the HfO2 high-k main dielectric layer is formed on the surface of the AlON interface layer. Experimental results show that the composite material provided by the invention has a dielectric constant of 15-30, a forbidden bandwidth of greater than 5eV, an interface state density of less than 1 * 10 < 12 > cm <-2 > eV <-1 > and a breakdown field strength of 7MV / cm-15MV / cm, can effectively improve the interface characteristics of a beta-Ga2O3 MOS power device when being used for the beta-Ga2O3 MOS power device, improves the reliability of a gate medium, and is suitable for being applied to high-voltage and high-temperature power devices.

This invention relates to the field of optoelectronic manufacturing technology, specifically disclosing a Micro-LED chip and its fabrication method. The fabrication method includes: forming an epitaxial layer on a substrate; forming conductive steps and isolation trenches on the epitaxial layer to obtain a first intermediate; immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain a second intermediate; the silane coupling agent contains a first active group and a second active group, the first active group being methoxy or ethoxy, and the second active group being amino; heat-treating the second intermediate in an inert atmosphere for a second preset time to obtain a third intermediate; forming a protective layer on the third intermediate; the protective layer's E... g ≥4.0 eV; A first through-hole and a second through-hole are formed on the protective layer to obtain a fourth intermediate; A first electrode and a second electrode are formed on the fourth intermediate. Implementing this invention can improve the luminous efficiency and reliability of Micro-LED chips.

This invention provides a method for preparing a β-Bi₂O₃ / Bi₂O₂Se heterojunction and its photodiode via reverse airflow confinement growth, relating to the field of two-dimensional semiconductor materials and optoelectronic device fabrication technology. The method includes the following steps: S1. Providing a few-layer (or multi-layer) Bi₂O₂Se nanosheet; S2. Placing the Bi₂O₂Se nanosheet within a confinement space, which includes a cavity with an exhaust channel at the top and a heating platform with a reverse air supply port at the bottom; S3. Introducing a 10% (by volume) oxygen / argon mixture into the confinement space; S4. Oxidizing the Bi₂O₂Se nanosheet at an oxidation temperature of 260°C for 45 minutes to selectively generate a β-Bi₂O₃ layer with a thickness of 10–30 nm on its surface, thereby constructing a β-Bi₂O₃ / Bi₂O₂Se heterojunction structure at the interface; S5. Removing the heterojunction sample after cooling. Through the above steps, this method has the advantages of clear and stable heterojunction structure, significantly improved β-phase selective growth rate, greatly enhanced device performance, simple process, and strong compatibility.

The invention relates to a two-dimensional metal material for an ultraviolet photoelectric detector and a preparation method of the two-dimensional metal material, and belongs to the technical field of detector preparation, a sapphire substrate is activated through high-activity particles through plasma treatment, hydroxyl active sites are introduced, a clean interface foundation is laid for heteroepitaxial growth of an ultra-wide forbidden band Ga2O3 film, and the performance of the detector is improved. The method comprises the following steps: performing chemical vapor deposition on Ga2O3 to ensure the specific absorption capacity of Ga2O3 to ultraviolet light, annealing in a mixed atmosphere after chemical vapor deposition, repairing the oxygen vacancy defect of a Ga2O3 film by using the high activity of ozone, improving the crystallization quality, effectively reducing dark current noise, and performing in-situ growth of a WSe2 layer in a high vacuum environment through a pulse laser deposition technology to form a van der Waals heterojunction without lattice mismatch. And an efficient carrier separation channel can be constructed by virtue of energy level matching of WSe2 and Ga2O3, so that the problem that ultraviolet absorption and carrier transmission are difficult to consider by virtue of a single material is solved, and the light response capability of the device is remarkably enhanced.

This invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method. The digital alloy material comprises: a superlattice structure matching the crystal lattice of an InP substrate; the superlattice structure is formed by repeated stacking of single periodic units; each periodic unit comprises a layer, a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer stacked sequentially; wherein the value of x ranges from 0.75 to 0.85; the thickness ratio between the layer, the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer in a single periodic unit is 22:1:10:1. The digital alloy material and its preparation method provided by this invention can solve the problems of low n-type carrier concentration and narrow application range of n-type alloy materials in the multiplication region of avalanche photodiodes.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

A gate oxide process, first dry oxidation treatment, wet oxidation treatment and second dry oxidation treatment are carried out on the substrate in sequence, so that the silicon-chlorine bond is formed between the third oxide layer and the substrate, compared with only reducing the light doping leakage ion implantation dose and increasing the light doping leakage energy, the hydroxyl introduced by the wet oxidation treatment not only improves the chlorine activity, but also as a transport carrier makes the chlorine efficiently enriched in the new oxide layer, the high concentration of chlorine fills the oxygen vacancies, reduces the bulk trap density, the silicon-chlorine bond formed by the second dry oxidation treatment has a deeper trap energy level, which can reduce the interface state density and improve the device's ability to resist hot carrier damage. Moreover, the hydrogen introduced by the wet oxidation treatment is removed in the second dry oxidation treatment, thereby avoiding the situation that the silicon-hydrogen bond is broken, the hot carrier injection is intensified, and then the degradation chain reaction is triggered, thereby achieving the effect of improving the hot carrier injection effect.

This invention relates to the field of semiconductor technology, specifically to a method and device for controlling the interface of a gallium oxide diode based on ammonia plasma treatment. The key technical points are: providing a gallium oxide sample, the gallium oxide sample including a substrate and a gallium oxide drift layer formed on the substrate; fabricating an ohmic contact electrode in a predetermined electrode region of the gallium oxide sample; subjecting the sample after forming the ohmic contact electrode to ammonia plasma treatment to form an interface control region on the surface region of the gallium oxide drift layer; fabricating a diode electrode structure on the interface control region according to the target device structure, thereby obtaining a Schottky barrier diode, a heterojunction diode, or a heterojunction barrier Schottky diode; achieving the effects of improving the chemical state and defect distribution on the gallium oxide surface, reducing the interface state density, reducing the reverse leakage current, increasing the breakdown voltage, reducing the on-resistance, and improving the overall electrical performance of the device.

The present disclosure provides an etching solution, a GaN material etching method and a gallium nitride transistor manufacturing method, and belongs to the technical field of semiconductors. The etching solution comprises a tetramethylammonium hydroxide solution and an oxidizing agent, the concentration of the tetramethylammonium hydroxide solution is 0.1-2.0 mol / L, and the concentration of the oxidizing agent is 0.01-0.5 mol / L. The present disclosure can improve the etching effect of GaN materials.

The invention relates to the field of solar cells, in particular to a solar cell piece and a preparation method thereof, a laminated cell and a photovoltaic module, and the prepared solar cell piece comprises a silicon substrate, and an aluminum oxide interface modification layer, a tunneling oxide layer, a heavily doped polycrystalline silicon layer, a back passivation film layer and a back electrode which are sequentially arranged from the back of the silicon substrate from inside to outside, the front emitting electrode, the front passive film layer and the front electrode are sequentially arranged on the front face of the silicon substrate from inside to outside, and the thickness of the aluminum oxide interface modification layer is smaller than that of the tunneling oxide layer. According to the cell, the aluminum oxide interface modification layer is inserted between the back surface of the silicon wafer and the tunneling oxide layer, fixed negative charges and high dielectric constant of aluminum oxide are utilized, interface positive charges are neutralized, the interface state density is reduced, meanwhile, it is ensured that the electron tunneling efficiency is not affected, and the problem of insufficient passivation caused by Si-SiOX interface defects of an existing cell silicon wafer is solved; and finally, the conversion efficiency and the long-term stability of the battery and the manufactured photovoltaic module are improved.

The application provides an enhanced HEMT power tube device and a preparation method thereof, wherein a four-layer composite structure of a GaN protection-charge regulation layer, an AlN first etching stop layer, a P-type GaN main body layer and a P-type AlGaN top layer barrier layer is sequentially arranged from bottom to top, the P-type AlGaN top layer barrier layer is used to increase the Schottky barrier height, inhibit the positive forward current of the gate and improve the gate voltage resistance; the P-type GaN main body layer is used to realize the enhanced characteristics of the device by depleting the two-dimensional electron gas below, and the threshold voltage is controlled; the Al-F strong bond energy characteristics are used in the AlN first etching stop layer to realize etching self-stop, and the etching damage to the AlGaN barrier layer is reduced by the joint action of the GaN protection-charge regulation layer; the GaN protection-charge regulation layer is used to reduce the interface state density, reduce the dynamic on-resistance and reduce the occurrence of current collapse, and meanwhile, the gate edge electric field distribution is smoothed, and the breakdown voltage is improved. In addition, a first passivation layer, a source field plate, a second passivation layer and a floating field plate can be further formed, and the GaN protection-charge regulation layer is used to jointly act to relieve the electric field concentration, improve the voltage resistance and reliability of the gate.

The gallium nitride-based semiconductor laser comprises a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, a first upper limiting layer, an electron blocking layer, a second upper limiting layer and a contact layer which are sequentially arranged from bottom to top, and the lower waveguide layer comprises a first lower waveguide layer and a second lower waveguide layer. The first lower waveguide layer comprises a first upper waveguide layer and a second upper waveguide layer, the first lower waveguide layer is located below the second lower waveguide layer, the upper waveguide layer comprises a first upper waveguide layer and a second upper waveguide layer, the first upper waveguide layer is located below the second upper waveguide layer, and the second lower waveguide layer and the first upper waveguide layer form a strain waveguide layer. The strain waveguide layer forms V-shaped elastic coefficient distribution, V-shaped volume elastic modulus distribution and V-shaped thermal expansion coefficient distribution on the two sides of the active layer. The performance of the laser can be improved.

This invention discloses a gallium oxide field-effect transistor and its fabrication method, relating to the field of gallium oxide device technology. The gallium oxide field-effect transistor includes, from bottom to top, a drain, a gallium oxide substrate, a gallium oxide epitaxial layer, a gallium oxide current blocking layer, and an n-type electrode. + Type-n highly doped gallium oxide layer; n + The surface of the highly doped gallium oxide layer has grooves, the bottom of which abuts into the gallium oxide epitaxial layer; it also includes: a gallium oxide gate dielectric layer located on the bottom wall and sidewalls of the grooves and n + On a portion of the surface of a highly doped gallium oxide layer; the gate, located on the surface of the gallium oxide gate dielectric layer; the source, located on the n-type... + On the surface of a highly doped gallium oxide layer, this invention effectively solves the problem of a large number of dangling bonds failing to form due to lattice mismatch between the silicon oxide or aluminum oxide gate dielectric layer and gallium oxide, reduces the interface state density between the gate dielectric layer and gallium oxide, and effectively improves characteristics such as gate leakage current and threshold voltage drift.

The application discloses a preparation method of a TBC back contact solar cell multi-tunneling oxide layer, utilizes a multi-temperature zone LPCVD device, realizes whole-process precise temperature control from pretreatment to deposition and then to annealing, slow cooling transition and low-temperature interval of the whole deposition process, greatly reduces thermal stress and is suitable for sheeting production; through decomposing the deposition process into three sub-steps and accurately designing pressure environment, gas type, flow and duration of each sub-step, "programmable" growth of the structure, composition and doping concentration of the oxide layer from an interface to a bulk phase and then to a surface layer is realized; this is the core of realizing a high-performance multi-layer tunneling structure, high quality and high uniformity under low temperature; precise cooperation of temperature and gas sequence ensures that even under low temperature, a high-quality oxide layer with density, uniformity and low interface state density can be obtained, and a relatively wide process window and good repeatability are realized.