48results about How to "Reduce interface state density" patented technology

The invention provides a planar gate silicon carbide VDMOS capable of improving short circuit reliability and a preparation method, and the preparation method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming drain electrode metal; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a current sharing layer; forming a barrier layer on the drift layer, and performing etching and ion implantation to form a P-type well region and a low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region and a P-type source region are formed; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a first gate dielectric layer; depositing to form a second gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; and re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, and removing the barrier layer to complete preparation. And the heat conduction capability and the thermal reliability of the insulating medium are effectively improved.

The invention discloses a double-groove super junction structure and a manufacturing method thereof, the double-groove super junction structure comprises a plurality of MOS cells which are connected in parallel, and each MOS cell comprises a drain electrode, an upper metal source electrode, a grid electrode, a semiconductor epitaxial layer, a substrate layer, a P well layer and an N well layer; a groove is formed between adjacent MOS cells and in the middle of the heavily doped P well layer I through etching, an oxide layer is deposited at the bottom of the groove, a side metal source electrode is arranged on the surface of the oxide layer, and the top of the side metal source electrode is in contact with the upper metal source electrode; the side surface of the side metal source is in ohmic contact with the N well layer, the lightly doped P well layer I and the heavily doped P well layer I; the grid electrode is a longitudinal groove type grid electrode and is arranged between the two N well layers of the single MOS cell, and the grid electrode is connected with the N well layers, the first lightly-doped P well layer and the diffusion layer in an isolated mode through a grid oxide layer. According to the invention, the injection depth of the heavily doped P well layer I is increased through the groove, and the (11-20) surface channel is adopted, so that the interface state density is greatly reduced, and the overall size of the device is reduced.

The invention provides a method for reducing the interface state density of a SiC-MOS device and an MOS capacitor. The method comprises the following steps: providing a silicon carbide substrate; forming a silicon dioxide oxide layer on the silicon carbide substrate; pure oxygen annealing is carried out by adopting a rapid annealing process; pure nitrogen annealing is carried out by adopting a rapid annealing process; forming a gate electrode on the silicon dioxide oxide layer; and forming a substrate electrode at the bottom of the silicon carbide substrate to obtain the SiC-MOS capacitor. According to the invention, the two-step annealing process of low-pressure pure oxygen annealing and pure nitrogen annealing is carried out on the silicon dioxide (SiO2) / silicon carbide (SiC) interface, so that the device has relatively low interface state density and relatively high flat-band voltage stability.

The invention relates to the technical field of photovoltaic cell preparation, in particular to a cell assembly based on a rectangular silicon wafer and a processing method of the cell assembly. Comprising the following steps: placing a monocrystalline silicon wafer in a potassium hydroxide solution, texturing, washing and drying to obtain a textured silicon wafer; sequentially performing low-pressure diffusion, SE laser, polishing and oxidizing annealing on the textured silicon wafer to obtain a silicon wafer A; sequentially depositing an aluminum oxide layer and a silicon nitride layer on the back surface of the silicon wafer A to obtain a silicon wafer B; depositing a silicon nitride layer on the front surface of the silicon wafer B to obtain a rectangular silicon wafer; performing laser grooving, screen printing and sintering on the rectangular silicon wafer to obtain a single battery piece; the single battery pieces are connected in series through a welding strip to obtain a battery string; (3) sequentially laying glass, POE / EPE, a battery string, EVA and grid glazed backboard glass, sealing the edge by an edge sealing tape machine, and then, carrying out lamination, framing and junction box installation in the next process; and thus, a rectangular silicon wafer battery assembly is obtained.

The application provides a TOPCon cell and a preparation method thereof and a photovoltaic system, and relates to the field of solar cells. The TOPCon cell comprises a P-type silicon-based substrate and an N+ layer. The surface of the P-type silicon-based substrate extends in a direction away from the P-type silicon-based substrate and comprises, in sequence from the P-type silicon-based substrate, an N+ emitter layer, a silicon oxide layer, a first aluminum oxide layer, and a second aluminum oxide layer. The first aluminum oxide layer comprises a boron-doped aluminum oxide layer, and the second aluminum oxide layer comprises a phosphorus-doped aluminum oxide layer. The TOPCon cell adopts a double-layer gradient-doped aluminum oxide structure. The first aluminum oxide layer close to the P-type silicon-based substrate is a nanocrystalline aluminum oxide doped with boron, the B-O bond is used to enhance the interface chemical passivation, and the density of silicon dangling bonds is reduced. The second aluminum oxide layer close to the N+ emitter layer is an amorphous aluminum oxide doped with phosphorus. The phosphorus doping concentration gradient decreases, the electric field distribution can be controlled by P doping, and the hole recombination is inhibited.

The invention provides a super junction diode and a manufacturing method thereof, and relates to the technical field of semiconductors. The super junction diode comprises an N-type epitaxial wafer; the terminal region and the active region are located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, and each first P column comprises a P-type side wall, and a low-doped N-type ion region, a first insulating dielectric layer and a second insulating dielectric layer which are positioned in the P-type side wall; the first insulating dielectric layer and the second insulating dielectric layer are made of different materials; the first insulating dielectric layer is made of a material with a low dielectric constant or high dielectric strength; a passivation protection layer located on the surface of the terminal area; the first metal layer is located on the surface of the active region; and the second metal layer is located on the back of the epitaxial wafer. The super junction diode and the manufacturing method thereof provided by the invention have the advantages that the thermal failure probability of the device is reduced, and the breakdown voltage, reliability and robustness of the device are improved.

The invention provides an LED epitaxial structure and a preparation method thereof, and the LED epitaxial structure sequentially comprises a buffer layer, a cut-off layer, a first-type semiconductor layer, an active layer and a second-type semiconductor layer which are located on a substrate from bottom to top. Wherein the second type semiconductor layer sequentially comprises a second type limiting layer, a second type transition layer, a second type current expansion layer and a second type ohmic contact layer from bottom to top. Through the arrangement of the second type transition layer, the problem of material mismatch of the LED can be solved, and the performance of the LED is improved.

The present invention belongs to the field of electricity, and in particular to the field of H01B1 / 16, and more specifically to a conductive silver paste for the back side grid of N-type TOPCon and a preparation method thereof. The raw materials for its preparation include at least 85-95% of monodisperse spherical silver powder, 2%-3% of lead bismuth telluride main glass, 0.1-0.3% of lead boron auxiliary glass, 0.05-0.2% of silicon powder, and 2%-10% of organic adhesive. The N-type TOPCon solar cell prepared by the present invention not only has a lower contact resistance and saturation current density value, but also can improve the open circuit voltage, short circuit current, filling factor, etc., thereby improving the photoelectric conversion efficiency of the solar cell.

The invention provides a high-k gate dielectric composite material, a preparation method thereof and a beta-Ga2O3 MOS (Metal Oxide Semiconductor) power device. The composite material comprises a beta-Ga2O3 substrate; the SiO2 interface buffer layer is formed on at least one surface of the beta-Ga2O3 substrate; the Al2O3 transition layer is formed on the surface of the SiO2 interface buffer layer; the AlON interface layer is formed on the surface of the Al2O3 transition layer; and the HfO2 high-k main dielectric layer is formed on the surface of the AlON interface layer. Experimental results show that the composite material provided by the invention has a dielectric constant of 15-30, a forbidden bandwidth of greater than 5eV, an interface state density of less than 1 * 10 < 12 > cm <-2 > eV <-1 > and a breakdown field strength of 7MV / cm-15MV / cm, can effectively improve the interface characteristics of a beta-Ga2O3 MOS power device when being used for the beta-Ga2O3 MOS power device, improves the reliability of a gate medium, and is suitable for being applied to high-voltage and high-temperature power devices.

The invention relates to a process method for improving channel mobility and gate dielectric layer reliability of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The process method comprises the following steps of: forming a channel layer on an epitaxial layer by adopting ion implantation; carrying out surface treatment on the SiC epitaxial layer in a sacrificial oxidation mode; forming SiO2 on the surface of SiC by adopting a low-pressure chemical vapor deposition process to serve as a gate dielectric layer; and performing an NO post-deposition annealing process on the gate dielectric layer. The SiC / SiO2 interface roughness formed by the method is reduced, the problem that carbon clusters and carbon particles are generated in traditional thermal oxidation is avoided, and the interface state density is reduced, so that the channel carrier mobility is enhanced; besides, a step-by-step low-pressure chemical vapor deposition process is adopted, gate dielectric layer densification is carried out in a gap between two or more stages of deposition processes, residues of a precursor in deposition are fully decomposed, stress of the gate dielectric layer is released, the electric leakage level of the gate dielectric layer is reduced, the reliability of the gate dielectric layer is enhanced, and the device yield is improved.

The invention relates to the field of electronic devices, in particular to a transistor with a top gate structure, a preparation method of the transistor and electronic equipment. The preparation method comprises the following steps: providing a substrate with a two-dimensional material layer on the surface; forming a patterned source electrode and a patterned drain electrode on the two-dimensional material layer; sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in an area between the source electrode and the drain electrode; the buffer layer is removed, so that the two-dimensional material layer and the seed layer are in unstressed and nondestructive contact; and sequentially forming a dielectric layer and a top gate on the seed layer to obtain the transistor with the top gate structure. According to the method, stress-free and damage-free integration of the two-dimensional material and the high-dielectric-constant dielectric medium is achieved, the two-dimensional material-dielectric medium interface state density is reduced, and good grid control performance is guaranteed.

The invention discloses a preparation method of a solar cell. The preparation method comprises the steps of providing a silicon substrate; forming a first tunneling oxide layer on the first surface of the silicon substrate; forming a first conductive type semiconductor layer on the first tunneling oxide layer; forming a first transparent conductive layer on the first conductive type semiconductor layer; forming a first metal electrode layer on the first transparent conductive layer, and forming ohmic contact between a first metal electrode in the first metal electrode layer and the first transparent conductive layer; forming a second tunneling oxide layer on the second surface of the silicon substrate; forming a second conductive type semiconductor layer on the second tunneling oxide layer; forming a second transparent conductive layer on the second conductive type semiconductor layer; and forming a second metal electrode layer on the second transparent conductive layer, and forming ohmic contact between a second metal electrode in the second metal electrode layer and the second transparent conductive layer. The invention also discloses a solar cell.

The present application discloses a heterojunction battery and a method for manufacturing the same, and relates to the field of photovoltaic technology. The heterojunction battery includes a first transparent conductive layer, an n-type doped silicon layer, a first intrinsic silicon layer, a silicon wafer layer, a second intrinsic silicon layer, an oxide layer, a p-type doped silicon layer, and a second transparent conductive layer stacked in sequence, and the heterojunction battery also includes a first electrode and a second electrode, the first electrode is arranged in the first transparent conductive layer, and the second electrode is arranged in the second transparent conductive layer, wherein the oxide layer includes a p-type silicon oxide layer, and the thickness of the oxide layer is 0.5~2.5nm. By inserting a p-type silicon oxide layer between the second intrinsic silicon layer and the p-type doped silicon layer, the energy band discontinuity can be reduced and the fill factor of the battery can be improved. At the same time, since a tunneling path is provided, the hole carrier mobility can be improved.

This invention relates to the field of optoelectronic manufacturing technology, specifically disclosing a Micro-LED chip and its fabrication method. The fabrication method includes: forming an epitaxial layer on a substrate; forming conductive steps and isolation trenches on the epitaxial layer to obtain a first intermediate; immersing the first intermediate in a modified solution containing a silane coupling agent and reacting for a first preset time to obtain a second intermediate; the silane coupling agent contains a first active group and a second active group, the first active group being methoxy or ethoxy, and the second active group being amino; heat-treating the second intermediate in an inert atmosphere for a second preset time to obtain a third intermediate; forming a protective layer on the third intermediate; the protective layer's E... g ≥4.0 eV; A first through-hole and a second through-hole are formed on the protective layer to obtain a fourth intermediate; A first electrode and a second electrode are formed on the fourth intermediate. Implementing this invention can improve the luminous efficiency and reliability of Micro-LED chips.

This invention provides a method for preparing a β-Bi₂O₃ / Bi₂O₂Se heterojunction and its photodiode via reverse airflow confinement growth, relating to the field of two-dimensional semiconductor materials and optoelectronic device fabrication technology. The method includes the following steps: S1. Providing a few-layer (or multi-layer) Bi₂O₂Se nanosheet; S2. Placing the Bi₂O₂Se nanosheet within a confinement space, which includes a cavity with an exhaust channel at the top and a heating platform with a reverse air supply port at the bottom; S3. Introducing a 10% (by volume) oxygen / argon mixture into the confinement space; S4. Oxidizing the Bi₂O₂Se nanosheet at an oxidation temperature of 260°C for 45 minutes to selectively generate a β-Bi₂O₃ layer with a thickness of 10–30 nm on its surface, thereby constructing a β-Bi₂O₃ / Bi₂O₂Se heterojunction structure at the interface; S5. Removing the heterojunction sample after cooling. Through the above steps, this method has the advantages of clear and stable heterojunction structure, significantly improved β-phase selective growth rate, greatly enhanced device performance, simple process, and strong compatibility.

The invention discloses a negative capacitance transistor with a kappa-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a preparation method of the negative capacitance transistor. The negative capacitance transistor comprises a substrate, a GaN buffer layer, a UID-GaN channel layer, an Al < 0.25 > Ga < 0.75 > N barrier layer, a source electrode, a drain electrode and a grid electrode which are arranged on the Al < 0.25 > Ga < 0.75 > N barrier layer, and a kappa-Ga < 2 > O < 3 > / Al < 2 > O < 3 > composite iron dielectric layer which is arranged between the grid electrode and the Al < 0.25 > Ga < 0.75 > N barrier layer, wherein the substrate, the GaN buffer layer, the UID-GaN channel layer and the Al < 0.25 > Ga < 0.75 > N barrier layer are sequentially arranged from bottom to top. The negative capacitance transistor provided by the invention can realize the combination of volatile storage and non-volatile storage, so that the stability of a system and the reliability of data storage after power failure are improved while the high-speed data processing capability is ensured, and efficient data management support is provided for the application of a full reserve pool.

The invention relates to a two-dimensional metal material for an ultraviolet photoelectric detector and a preparation method of the two-dimensional metal material, and belongs to the technical field of detector preparation, a sapphire substrate is activated through high-activity particles through plasma treatment, hydroxyl active sites are introduced, a clean interface foundation is laid for heteroepitaxial growth of an ultra-wide forbidden band Ga2O3 film, and the performance of the detector is improved. The method comprises the following steps: performing chemical vapor deposition on Ga2O3 to ensure the specific absorption capacity of Ga2O3 to ultraviolet light, annealing in a mixed atmosphere after chemical vapor deposition, repairing the oxygen vacancy defect of a Ga2O3 film by using the high activity of ozone, improving the crystallization quality, effectively reducing dark current noise, and performing in-situ growth of a WSe2 layer in a high vacuum environment through a pulse laser deposition technology to form a van der Waals heterojunction without lattice mismatch. And an efficient carrier separation channel can be constructed by virtue of energy level matching of WSe2 and Ga2O3, so that the problem that ultraviolet absorption and carrier transmission are difficult to consider by virtue of a single material is solved, and the light response capability of the device is remarkably enhanced.

This invention provides an n-type digital alloy material for the multiplication region of an avalanche photodiode and its preparation method. The digital alloy material comprises: a superlattice structure matching the crystal lattice of an InP substrate; the superlattice structure is formed by repeated stacking of single periodic units; each periodic unit comprises a layer, a first GaAsSb layer, an n-type Si-doped GaAsSb layer, and a second GaAsSb layer stacked sequentially; wherein the value of x ranges from 0.75 to 0.85; the thickness ratio between the layer, the first GaAsSb layer, the n-type Si-doped GaAsSb layer, and the second GaAsSb layer in a single periodic unit is 22:1:10:1. The digital alloy material and its preparation method provided by this invention can solve the problems of low n-type carrier concentration and narrow application range of n-type alloy materials in the multiplication region of avalanche photodiodes.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

The invention discloses a field effect transistor and a preparation method thereof, the field effect transistor comprises a substrate, a drift layer, a silicon matrix region and a gate structure, the drift layer and the substrate have the same doping type, and one side, away from the substrate, of the drift layer is provided with a first surface; the plurality of silicon substrate regions are located on the two sides of the drift layer, the surfaces of the sides, away from the substrate, of the silicon substrate regions are located in the first surface or located on the side, away from the substrate, of the drift layer, the silicon substrate regions make contact with the gate oxide layer, and the silicon substrate regions are of the second doping type; the gate structure is at least partially located on the side, away from the substrate, of the drift layer and comprises a gate oxide layer, and the gate oxide layer makes contact with the multiple silicon substrate regions. According to the silicon carbide MOSFET, the interface state density between the silicon substrate region and the gate oxide layer is small, the electron mobility is high, and the resistance of electrons flowing through a channel is very small, so that the conduction resistance and conduction loss of the silicon carbide MOSFET are reduced.

The present invention discloses a semiconductor device and a manufacturing method thereof, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, the substrate comprising a channel region, a source region and a drain region, etching part of the substrate to form a plurality of recesses in the channel region; forming a continuous epitaxial compensation layer on the substrate in the recesses and the channel region, the surface of the epitaxial compensation layer having a plurality of protrusions along the length direction of the device, the length direction being the direction from the source region to the drain region; forming a gate on the epitaxial compensation layer; forming a source electrode in the source region on one side of the gate; and forming a drain electrode in the drain region on one side of the gate. The semiconductor device and the manufacturing method thereof provided by the present invention can reduce the area of ​​the semiconductor device, improve the utilization rate of the substrate, and improve the performance of the semiconductor device at the same time.

A gate oxide process, first dry oxidation treatment, wet oxidation treatment and second dry oxidation treatment are carried out on the substrate in sequence, so that the silicon-chlorine bond is formed between the third oxide layer and the substrate, compared with only reducing the light doping leakage ion implantation dose and increasing the light doping leakage energy, the hydroxyl introduced by the wet oxidation treatment not only improves the chlorine activity, but also as a transport carrier makes the chlorine efficiently enriched in the new oxide layer, the high concentration of chlorine fills the oxygen vacancies, reduces the bulk trap density, the silicon-chlorine bond formed by the second dry oxidation treatment has a deeper trap energy level, which can reduce the interface state density and improve the device's ability to resist hot carrier damage. Moreover, the hydrogen introduced by the wet oxidation treatment is removed in the second dry oxidation treatment, thereby avoiding the situation that the silicon-hydrogen bond is broken, the hot carrier injection is intensified, and then the degradation chain reaction is triggered, thereby achieving the effect of improving the hot carrier injection effect.

This invention relates to the field of semiconductor technology, specifically to a method and device for controlling the interface of a gallium oxide diode based on ammonia plasma treatment. The key technical points are: providing a gallium oxide sample, the gallium oxide sample including a substrate and a gallium oxide drift layer formed on the substrate; fabricating an ohmic contact electrode in a predetermined electrode region of the gallium oxide sample; subjecting the sample after forming the ohmic contact electrode to ammonia plasma treatment to form an interface control region on the surface region of the gallium oxide drift layer; fabricating a diode electrode structure on the interface control region according to the target device structure, thereby obtaining a Schottky barrier diode, a heterojunction diode, or a heterojunction barrier Schottky diode; achieving the effects of improving the chemical state and defect distribution on the gallium oxide surface, reducing the interface state density, reducing the reverse leakage current, increasing the breakdown voltage, reducing the on-resistance, and improving the overall electrical performance of the device.

The present disclosure provides an etching solution, a GaN material etching method and a gallium nitride transistor manufacturing method, and belongs to the technical field of semiconductors. The etching solution comprises a tetramethylammonium hydroxide solution and an oxidizing agent, the concentration of the tetramethylammonium hydroxide solution is 0.1-2.0 mol / L, and the concentration of the oxidizing agent is 0.01-0.5 mol / L. The present disclosure can improve the etching effect of GaN materials.

The embodiment of the invention provides a TOPCon solar cell. The TOPCon solar cell comprises a silicon substrate, wherein the silicon substrate comprises a first surface; the first tunneling oxide layer, the first doped polycrystalline silicon layer, the first intrinsic polycrystalline silicon layer and the second doped polycrystalline silicon layer are sequentially stacked on the first surface of the silicon substrate in the first direction; the first tunneling oxide layer, the first doped polycrystalline silicon layer, the first intrinsic polycrystalline silicon layer and the second doped polycrystalline silicon layer jointly form a laminated passivation structure; and the doping concentration of the first doped polycrystalline silicon layer is lower than that of the second doped polycrystalline silicon layer. According to the technical scheme, the first intrinsic polycrystalline silicon layer is free of element doping, the doping elements in the second doped polycrystalline silicon layer are diffused into the first doped polycrystalline silicon layer, the doping elements are prevented from being diffused into the first doped polycrystalline silicon layer, the doping concentration of the doping elements of the first doped polycrystalline silicon layer can be kept low, and the electrical performance of the first doped polycrystalline silicon layer is optimized.

The utility model provides a structure for optimizing ohmic contact on the back surface of a GaN device through a sin insertion layer, which belongs to the technical field of GaN devices, and comprises a GaN substrate and a sin layer arranged on the back surface of the GaN substrate, the sin layer is provided with a concave-convex structure, and the concave-convex structure is provided with a concave-convex groove. The GaN substrate is provided with a concave-convex structure, the concave-convex structure is specifically protrusions formed on the surface of the sin layer, the GaN substrate is further provided with a metal contact layer, the metal contact layer makes contact with the concave-convex structure, the metal contact layer is provided with structures matched with the protrusions on the surface of the sin layer, and the sin layer and the metal contact layer are physically interlocked through the concave-convex structure. According to the utility model, the peeling phenomenon of the contact layer under the condition of high temperature or high pressure is solved, and the long-term reliability of the device is improved.

The invention relates to the technical field of semiconductor device manufacturing, in particular to a GaN-based HEMT device and a preparation method thereof, a gate dielectric layer of the GaN-based HEMT device is any one of a laminated gate dielectric and a single-layer gate dielectric, and the gate dielectric layer comprises any one of a GeN dielectric layer and a GeON dielectric layer. According to the GaN-based HEMT device, the leakage current of the gate dielectric layer can be effectively reduced, the voltage endurance capability of the device is improved, breakdown or damage is avoided, a high-quality interface structure can be formed, the adverse effect of an interface state on the performance of the device is reduced, and the efficiency and power performance of the GaN-based HEMT device are remarkably improved. Therefore, the selection range of the gate dielectric material of the GaN-based HEMT device is widened, the performance of the device is remarkably improved and the cost is reduced through fine material selection and structural design, and powerful support is provided for wide application of the GaN-based HEMT device.

The invention discloses a manufacturing method of an FDSOI device. The manufacturing method comprises the following steps: step 1, growing a first germanium-silicon layer on the surface of a top silicon layer of an SOI substrate; step 2, performing first oxidation to form a top silicon oxide layer on the surface of the first germanium-silicon layer; and step 3, annealing to enable germanium to be uniformly distributed in the top silicon layer and the first germanium-silicon layer and form a top germanium-silicon layer. And 4, removing the top silicon oxide layer. And 5, performing silicon treatment to enable unsaturated Ge bonds on the top surface of the top germanium-silicon layer to be saturated and combined by Si bonds and form a silicon-rich layer on the top surface of the top germanium-silicon layer. And step 6, second oxidation is carried out to form a gate oxide layer on the top surface of the top germanium-silicon layer, and the gate oxide layer is formed by combining Si bonds and oxygen in the silicon-rich layer, so that the number of Ge-O bonds is reduced, and the interface state density is reduced. According to the invention, the germanium concentration of the channel layer formed by the germanium-silicon material can be improved, and the interface state density between the channel layer and the gate oxide layer can be reduced, so that the performance of the device can be improved.

A composite dielectric structure of a gallium nitride electronic device includes: a low interface state dielectric insertion layer and a high breakdown electric field dielectric layer, wherein the low interface state dielectric insertion layer is grown on the surface of the gallium nitride electronic device, and the high breakdown electric field dielectric layer is grown on the low interface state dielectric insertion layer. The present disclosure also provides a method for preparing a composite dielectric structure, including: placing the gallium nitride electronic device in a machine, adjusting the temperature of the machine to a first preset temperature, adjusting the power to a first preset power, using plasma to clean the surface of the gallium nitride electronic device, adjusting the temperature of the machine to a second preset temperature, adjusting the power to a second preset power, growing a low interface state dielectric insertion layer on the surface of the gallium nitride electronic device, adjusting the temperature of the machine to a third preset temperature, adjusting the power to a third preset power, and growing a high breakdown electric field dielectric layer on the low interface state dielectric insertion layer. The present disclosure can effectively solve the problem of surface interface defects of gallium nitride electronic devices.

The present invention discloses a structure of an antimonide quantum well CMOS device and a preparation method thereof, belonging to the field of microelectronic technology. The device structure comprises: a substrate; a buffer layer is provided on the substrate; a p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are relatively independently provided on the buffer layer; a passivation isolation layer is provided between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer. The antimonide quantum well structure provided by the present invention can, on the one hand, reduce the dislocation density caused by lattice mismatch through component regulation, and on the other hand, effectively isolate the channel from the high-k gate medium through a barrier layer, and form a two-dimensional electron / hole gas on the channel surface, thereby improving the mobility and improving the device performance. The present invention also provides a method for preparing an antimonide quantum well CMOS device, which realizes the epitaxial growth of n-channel and p-channel materials of the same system.