6 results about "Recombination current" patented technology

This application discloses a method and apparatus for constructing a parallel current source model for IGBT turn-off current analysis. The main scheme is as follows: Based on the physical nature of the IGBT turn-off current decrease process, it is revealed that it includes two synchronously occurring sub-processes (the carrier injection process and the carrier recombination reduction process corresponding to MOSFET turn-off); the IGBT turn-off current is defined as the parallel superposition of the currents (injection current and recombination current) generated by these two sub-processes; this abstract "dual current" physical theory is transformed into an equivalent circuit composed of a controlled source and a current source connected in parallel; the two sub-processes are analyzed in this way: for the first sub-process, a first relationship characterizing the dynamic evolution law of the injection current is derived; for the second sub-process, a second relationship characterizing the dynamic evolution law of the recombination current is derived; finally, by combining these two relationships, a parallel current source model for quantitatively characterizing the IGBT turn-off current decrease process is constructed.

This invention discloses a P + -v-N + A novel mercury cadmium telluride mesa heterojunction infrared detector and its fabrication method, utilizing liquid-phase epitaxy to achieve P + -v material structure fabrication: N is prepared on the surface of the v-shaped layer using a back-implantation method. + After annealing, a three-layer hetero-doped material structure was fabricated, and P was then fabricated using device fabrication technology. + -v-N + This invention relates to a P-type mercury cadmium telluride mesa heterojunction detector. It utilizes the P-type wide-bandgap heterolayer growth process to achieve interfacial interdiffusion, reducing interface defect density and improving interface quality. Based on the ability to control raw material impurities above 7N and the self-purification characteristics of the growth process, it achieves stable control of low-concentration V-type layer impurities. Furthermore, it utilizes a high-resistivity transition layer formed by epitaxy and N-type metallurgical layer formed by boron ion implantation. + Layer; RTP fast annealing is used to repair injection damage. This invention can effectively suppress recombination current. Its surface heteromaterial forms a band modulation structure that suppresses tunneling current and surface leakage current. Compared with P-on-n devices, it can theoretically reduce dark current by two orders of magnitude and improve device performance.

This invention provides a TOPCon battery structure with two polycrystalline silicon layers and its fabrication method, relating to the field of battery processing technology. The TOPCon battery structure includes a monocrystalline silicon wafer, with a diffusion layer, a passivation layer, a front antireflection layer, and a front metal electrode sequentially disposed on the front side of the monocrystalline silicon wafer, and a tunneling layer, a doped polycrystalline silicon layer, a back antireflection layer, and a back metal electrode sequentially disposed on the back side of the monocrystalline silicon wafer. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon layer located on the back side and a second doped polycrystalline silicon layer located between the back metal electrode and the first doped polycrystalline silicon layer, wherein the doping concentration of the second doped polycrystalline silicon layer is greater than that of the first doped polycrystalline silicon layer. This invention overcomes the shortcomings of existing technologies, ensuring the thickness of the doped polycrystalline silicon in the metal contact area, preventing damage to the tunneling oxide layer during sintering, and reducing recombination current and contact resistance; simultaneously, it reduces photoparasitic absorption in the non-metallic region, especially reducing free carrier absorption.

This invention discloses a TOPCon battery and its fabrication method, belonging to the field of TOPCon battery technology. It includes a monocrystalline silicon wafer with a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer, and a back metal electrode sequentially disposed on its back side from the inside out. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon region and a second doped polycrystalline silicon region. The first doped polycrystalline silicon region is in contact with the back metal electrode and is disposed on the surface of a groove. The tunneling oxide layer is relatively thin, and the inward junction depth is greater than that of the second doped polycrystalline silicon region. This effectively prevents electrode metal from penetrating into the junction region, reduces metal recombination current, and improves the battery's open-circuit voltage. Furthermore, the first doped polycrystalline silicon region has a larger contact area with the printing paste, reducing the battery's contact resistance. Simultaneously, the groove prevents the printing paste from widening outward, ensuring a high grid line aspect ratio, reducing grid line resistance, and thus improving the battery's fill factor.

This invention provides a P-type passivated contact structure and its preparation method. The P-type passivated contact structure includes a silicon substrate, a first silicon oxide layer, a first polycrystalline silicon layer, a second polycrystalline silicon layer, and a hydrogen-containing dielectric layer. The silicon substrate has a diffusion region near the surface of the first silicon oxide layer. The surface of the first silicon oxide layer near the first polycrystalline silicon layer has a native pinhole defect structure generated by plasma bombardment. The first polycrystalline silicon layer is made of carbon-doped boron-containing polycrystalline silicon, wherein the boron and carbon doping concentrations gradually increase away from the first silicon oxide layer, and the thickness is greater than or equal to 8 nm. The second polycrystalline silicon layer is also made of carbon-doped boron-containing polycrystalline silicon, with a thickness greater than 10 nm. The interfacial silicon oxide surface of this invention has a high density of pinhole defects, and using carbon-doped boron-containing amorphous silicon as the source layer can reduce oxide layer defects caused by interfacial boron enrichment, achieving excellent surface passivation and selective carrier collection, and reducing surface recombination current density.

The application discloses a solar cell, a preparation method of the solar cell, a laminated cell and a photovoltaic module, and belongs to the technical field of semiconductors. The solar cell comprises a semiconductor substrate and a first locally heavily doped semiconductor layer located on a main surface of the semiconductor substrate. The first locally heavily doped semiconductor layer has the same or opposite conductivity type as the semiconductor substrate, and the doping concentration of an edge region of the first locally heavily doped semiconductor layer is higher than that of a central region. The doping concentration of the first locally heavily doped semiconductor layer is optimized and designed, so that the doping concentration of the edge region is higher than that of the central region, thereby effectively inhibiting the serious carrier recombination phenomenon existing at the edge of the contact window of the locally doped semiconductor layer, fundamentally strengthening the field effect passivation ability of the edge, and effectively reducing the edge recombination current density to a very low level and improving the open circuit voltage and the fill factor of the cell.