Disclosed is a serial to parallel conversion circuit in which the shift
clock frequency is lowered to close to the frequency on the data line to achieve
low power dissipation. The serial to parallel conversion circuit at least includes a
shift register (FF1 to FFn), to the first stage of which is entered a data transfer
start signal STPO and which sequentially transfers the data transfer
start signal by input shift
clock signal, a plural number of latch circuits (LT1 to LTn) receiving signals sequentially output from the
shift register as latch
clock signal to latch a
data signal serially supplied to a data line, and control circuits (Con1 and Con2) receiving at least shift
clock signal CLKO supplied to flip-
flops and the output signals of the flip-
flops. If, in case the output signals of the flip-
flops are in active states, the shift
clock signal supplied to the flip-flops undertakes a transition to an inactive state, the control circuits reset the flip-flops to inactivate the output signals of the flip-flops. The neighboring ones of the flip-flops sample and output signals entered to the data terminals, using one and the other of the rising and falling edges of the shift
clock signal supplied from the clock line. The shift clock
signal is operated at a frequency equal to one-half the
data signal transfer frequency.