79results about "Semiconductor characterisation" patented technology

The invention provides a gate-source short-circuit SiC MOS device failure analysis method and related equipment, and the method comprises the steps: responding to the determination that the functional characteristics of a source and a drain have no abnormal conditions, carrying out the analysis of the cause of a short-circuit fault of a gate and the source based on the characteristics of a silicon carbide material and an MOS device failure mechanism, and carrying out the analysis of the short-circuit fault of the gate and the source. Comprising the following steps: judging whether gate source chemical lap joint caused by internal water vapor exists or not through a dry chip; unsealing the chip to expose the interior of the chip, testing the chip, and judging whether a metallization layer migration short circuit caused by high temperature occurs or not; analyzing whether breakdown caused by high electric field stress exists in the gate oxide layer; according to the failure analysis method provided by the invention, the reason of the failure of the SiC MOS device can be accurately analyzed, and the problem that the microdefect of the SiC MOS device cannot be positioned by a traditional means is solved.

The invention provides a method and a device for testing electrical characteristics of a semiconductor. The method comprises the following steps: acquiring a semiconductor micro Hall test structure comprising at least one doping element; measuring electrical parameters of the test structure; removing a thin layer with a specific thickness from the test structure by using secondary ion mass spectrometry, and carrying out atomic composition analysis on the removed material; measuring the electrical parameters of the test structure again; and repeating the two steps until the distribution information of the doping concentration of the active doping element and the initial doping element in the test structure is obtained, and calculating the distribution information of the doping efficiency of the test structure according to the distribution information of the doping concentration. According to the application, the electrical characteristics and the doping concentration can be combined, and the distribution of the doping efficiency can be inferred by acquiring the distribution information of the electrical characteristics and the doping concentration of the semiconductor; and a thin layer is controllably removed through a secondary ion mass spectrometry technology, and semiconductor doping contour information with higher precision is obtained.

The application discloses a method for testing diffusion depth by voltage method, which comprises the following steps: firstly, oxidizing the upper part of a silicon substrate; secondly, performing photoetching on the oxide layer according to a designed layout, wherein the shape of the photoetching pattern is square and the photoetching patterns are distributed in an array, the interval between two adjacent photoetching patterns in each row is increased in turn, and the interval between two adjacent rows is greater than the maximum value of the interval between any two adjacent photoetching patterns in the two rows; thirdly, removing the oxide layer in the photoetching area and photoresist used in the photoetching; fourthly, injecting or doping impurities into the photoetching area of the silicon substrate, and then removing the surface oxide layer; fifthly, connecting two probes with a graphic instrument, and testing the two adjacent photoetching patterns on the sample in the order of the interval from small to large; sixthly, continuing to test the next two adjacent photoetching patterns when the sample is broken down; and seventhly, recording the interval of the last two adjacent photoetching patterns when the sample cannot be broken down, and then obtaining the diffusion depth by combining the ratio of the lateral diffusion distance of the impurities to the diffusion depth, so that the method has low cost and wide application range.

The invention relates to the technical field of semiconductor material preparation, and discloses a preparation and passivation process of a carrier decay time standard sample wafer, which comprises the following steps: preparing a passivation precursor solution; carrying out pretreatment on the semiconductor substrate; applying the passivation precursor solution to the surface of the semiconductor substrate in a spin-coating deposition mode to form a wet film; performing low-temperature gelation treatment on the wet film to form a solid gel film; two-stage annealing treatment is carried out on the semiconductor substrate with the solid gel film, the first-stage annealing is carried out in a high-purity nitrogen atmosphere carrying heavy water vapor, and the second-stage annealing is carried out in a high-purity dry nitrogen atmosphere; and cooling the semiconductor substrate subjected to the two-stage annealing treatment. The passivation layer with high stability, long service life and low cost is prepared through heavy water vapor passivation and two-stage annealing processes.

A multilayer test sample includes a stack having a bottom layer, a top layer, and a tunnel layer sandwiched between the bottom and top layers. The multilayer test sample has terminals below the stack for performing measurements on the stack. The positions of the terminals or the distances between them are unknown. A model and measurement strategy are defined to allow determination of material parameters of the stack.

The invention belongs to the technical field of reliability analysis of devices, and particularly relates to a quantitative analysis method for migration characteristics of an indium component in an epitaxial wafer. Comprising the following steps: providing epitaxial wafers with consistent initial characteristics, and carrying out uniform cleavage; taking one small block as a reference sample, and performing external disturbance treatment on other small blocks; the method comprises the following steps: respectively carrying out non-destructive structure characterization treatment on a reference sample and a sample subjected to external disturbance treatment, including high-resolution X-ray diffraction test, photoluminescence and cathode fluorescence combined test and time-resolved photoluminescence spectrum measurement; comprising high-resolution transmission electron microscope and EDS energy spectrum combined imaging and secondary ion mass spectrum; finally, FP lasers are prepared respectively, and electrical characterization processing is carried out. And quantitatively analyzing the influence of indium component migration on the electrical properties of the FP laser according to the result. The method has the advantages that the migration of indium atoms is analyzed according to a method for changing the microstructure in the quantum well and changing the dynamic behavior of a carrier.

The application discloses a kind of gallium nitride-based double heterojunction HEMT field effect mobility characterization method, including the HEMT to be tested is prepared as the HEMT of fat-FET structure, wherein the HEMT to be tested is gallium nitride-based double heterojunction HEMT, the HEMT of fat-FET structure is the gallium nitride-based double heterojunction HEMT of fat-FET structure.Canal conductance test is carried out to the HEMT of fat-FET structure;The CV characteristic curve of the HEMT of fat-FET structure is tested to obtain first capacitance-voltage variation curve;First capacitance-voltage variation curve is processed by addition;According to preset formula, the field effect mobility-gate voltage curve of upper channel and lower channel is obtained;The electron surface density-gate voltage curve of upper channel and lower channel is obtained respectively;The field effect mobility-electron surface density curve of upper channel and lower channel is obtained respectively.The application can characterize the specific field effect mobility of upper channel and lower channel respectively, improve the characterization accuracy of the field effect mobility of gallium nitride-based double heterojunction HEMT, and be beneficial to the characteristic analysis and process optimization of gallium nitride-based double heterojunction HEMT.

The invention discloses semiconductor crystal ingot detection equipment, which comprises a first type of test electrode, a second type of test electrode, a third type of test electrode, a fourth type of test electrode and a fifth type of test electrode, the second type of test electrode is used for being disconnected from the crystal ingot on the other side of the crystal ingot; and the electrical parameter testing device is electrically connected with the first type of testing electrodes and the second type of testing electrodes respectively, so that the electrical parameter testing device detects voltage or current between the first type of testing electrodes and the second type of testing electrodes. The semiconductor crystal ingot detection equipment has the beneficial effects that the semiconductor crystal ingot detection equipment is simple and reliable in structure and can effectively detect the electrical parameters of the crystal ingot.

Methods for characterizing semiconductor doping in wide-bandgap semiconductor samples include: measuring an initial value V0 of the surface voltage at a region on the surface of the semiconductor sample in darkness; charging the region to deep depletion in darkness by depositing a specified corona charge at the region; measuring the surface voltage value at the region in darkness after charging; and using a specific photon flux f. eff The light irradiates the charging region, and a specific photon flux f eff A photon energy above the semiconductor bandgap is used, sufficient to generate free minority carriers in the semiconductor sample, thereby causing photoneutralization of the corona charge. The relationship between the photoneutralization-induced corona charge decay and the irradiation time t at the region is monitored using non-contact time-resolved measurements of the surface voltage V(t). The monitored time-resolved surface voltage decay data V(t) is analyzed to determine the photoneutralization time constant τ. ph ; and using a specific photon flux f eff Light neutralization time constant τ ph It serves as a semiconductor doping index, and its value characterizes the semiconductor doping concentration in that region.

A position measurement method includes: performing a calibration operation; and measuring a position of a stage according to a mapping table so as to control movement of the stage during an inspection operation. Performing the calibration operation includes: moving the stage along an axis; measuring N sets of first values, wherein each set of first values includes a first distance between a first mirror and a first laser interferometer and a second distance between the first mirror and a second laser interferometer; measuring N sets of second values, wherein each set of second values includes a third distance between a second mirror and a third laser interferometer and a fourth distance between the second mirror and a fourth laser interferometer; obtaining a flatness profile of the first mirror along the axis according to the first values and the second values; and generating the mapping table according to the flatness profile.

To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. A semiconductor device includes an n-type SiC layer having a first surface, a second surface, and end faces, a p-type voltage relaxing layer formed in the SiC layer so as to be exposed to the end portion of the first surface of the SiC layer, an insulating layer formed on the SiC layer so as to cover the voltage relaxing layer, and an anode electrode that is connected to the first surface of the SiC layer through the insulating layer and has a pad area selectively exposed.

The invention relates to various devices and methods for preventing the injection of a substrate current into the substrate sub of a CMOS circuit. For this purpose, the devices implement different methods for preventing such injection. They detect the potential of a contact (PDH, PDL) of the integrated CMOS circuit, compare the value of the detected potential with a reference value, and connect the contact (PDH, PDL) to a leakage circuit node (ABK) to drain the current, so that it does not flow through the parasitic bipolar lateral structure, i.e., not into the substrate. The leakage circuit node can be connected, for example, to the reference potential line (GND) or to another line that has a higher potential than that of the reference potential line (GND). This electrical connection is then activated or...initiated when the value of the contact potential (PDH, PDL) is below or equal to a reference value, where this reference value is below the potential of the substrate Sub and / or below the potential of the reference potential line (GND) or the other line mentioned above.

The application discloses a kind of semiconductor material eddy conductivity testing methods with cooling function, including the silicon wafer to be measured motion to be measured site, the conductivity probe is moved to the measured site, while using the cooling spray head cooling spray, according to the vortex cold gas calibration curve, determine the gas supply amount required to be provided by the cooling spray head, while according to the standard relationship curve between the current in the existing passive coil and the conductivity of the standard silicon wafer determines the conductivity of the measured site;The application utilizes the hollow part of active electromagnetic coil, by installing cooling spray head in hollow part, according to the heat quantity of material, a certain flow and pressure cooling air is passed in, the heat of semiconductor material surface is promptly exported, ensure that the temperature of semiconductor material surface is in specified range, improve the measurement accuracy of conductivity tester.

A method for determining electronic band structure includes partitioning, based on a location of each of a plurality of atoms forming a crystalline structure, a volume of the crystalline structure to obtain Voronoi tessellations. The method also includes constructing, based on the Voronoi tessellations, a plurality of crystal graphs and deriving, based on the plurality of crystal graphs, one or more local structural features of the crystalline structure. The method also includes feeding, into a trained machine-learning model, the one or more local structural features, one or more global structural features of the crystalline structure, and one or more species-based features of the crystalline structure. The trained machine-learning model, in response to said feeding, returns a plurality of energy values that sample a Brillouin zone of the crystalline structure.

The multi-layer test specimen includes a stack having a bottom layer, a top layer, and a tunnel layer sandwiched between the bottom and top layers. The multi-layer test specimen has terminals below the stack for measurements on the stack. The terminals have unknown positions or distances between the terminals. A model and measurement strategy are defined such that material parameters of the stack may be determined.

The invention relates to a circuit for monitoring degradation of a semiconductor device. A system includes a semiconductor device including a source terminal, a drain terminal, and an interface layer between the source terminal and the drain terminal, the interface layer including a plurality of interface channels. The system also includes a degradation monitoring circuit including an electrical sensor, where the degradation monitoring circuit is configured to: generate, using the electrical sensor, a sensor signal corresponding to one or more of the plurality of interface channels; determining whether there is a degradation of the material at one or more of the plurality of interface channels based on the sensor signal; and outputting information indicating whether there is a degradation of the material at one or more of the plurality of interface channels.

The invention relates to the technical field of semiconductor material detection equipment, and discloses a broadband microwave probe device for measuring attenuation characteristics of current carriers. The outer wall of the detection pen is fixedly connected with a limiting ring, and one end of the detection pen is provided with a probe; the switching mechanism is mounted on one side of the probe pen; the switching mechanism comprises a limiting frame; the lifting mechanism is mounted on one side of the lifting mechanism; the moving mechanism is installed on one side of the moving mechanism, and the moving mechanism is connected with a supporting table through a supporting column; the fixing mechanism is mounted in the supporting table; the adjusting mechanism is mounted in the same side of the supporting table and the fixing mechanism; and the feeding mechanism is mounted on the upper surface of the supporting table. A limiting frame is driven to move through movement of a second connecting frame, the limiting frame pushes a first limiting rod, one end of the first limiting rod rotates in the limiting frame, then a fixing plate is pulled to be taken out of the limiting frame, and the effect of replacing the probe is achieved.

The invention relates to the technical field of semiconductor manufacturing and testing, in particular to a wafer edge sheet resistance testing method based on an eddy current method probe, and the method comprises the steps: 1, scanning a wafer according to computer vision, and carrying out the modeling of the wafer; step 2, digital twinning construction and synchronous calibration; step 3, pre-simulation and edge correction library construction; step 4, motion control and real-time edge processing; 5, dynamic compensation and square resistance calculation are carried out; step 6, generating a full-wafer sheet resistance distribution map and outputting data; step 7, testing data feedback and model iterative optimization; according to the method, the wafer-equipment integrated digital twinborn model is constructed, and the probe coordinate-edge effect correction coefficient mapping relation library is pre-established by utilizing finite element simulation, so that accurate dynamic compensation can be performed for near-edge vortex field distortion in an actual test; the systematic measurement error caused by incomplete physical field in the edge area in the traditional eddy current method is effectively overcome, and the accuracy and repeatability of the edge sheet resistance test are remarkably improved.

Provided is a device and method for measuring the diffusion coefficient of nanoscale minority carriers of semiconductor materials. The measuring device includes: a light source assembly for generating monochromatic light and pulsed light; a sample stage for carrying a semiconductor sample or a graphite sample; a conductive needle tip for approaching a surface target area of ​​a semiconductor sample or a graphite sample carried on the sample stage, and spaced apart from the semiconductor sample or the graphite sample; and a scanning Kelvin probe microscope connected to the conductive needle tip, and used to obtain a first contact potential difference and a second contact potential difference on the conductive needle tip approaching the surface target area in the absence of light and when monochromatic light is applied, respectively, and used to obtain a third contact potential difference on the conductive needle tip approaching the graphite sample; a spectral detector for obtaining the lifetime of minority carriers in the surface target area when pulsed light is applied; and a calculation device for calculating the diffusion coefficient according to the first contact potential difference, the second contact potential difference, the third potential difference, and the lifetime of minority carriers.

The application discloses a kind of carrier effective diffusion length test method and test system.The test method includes: providing first epitaxial structure and second epitaxial structure;Make laser respectively irradiation produce photo-generated carrier, diffuse to multiple quantum well layer and produce recombination luminescence, form photoluminescence spectrum;Based on photoluminescence spectrum, obtain first photoluminescence intensity, second photoluminescence intensity;Based on the correlation with the thickness of corresponding test layer, calculate the carrier effective diffusion length in test layer.The test method provided by the application does not need to cut the fragment, is more convenient for practical application, and is also expected to be used for whole piece multi-point scanning type test;Test cost is low, method is simple, and operability is strong;Evaluation obtained is the carrier effective diffusion length in test layer, reflects the carrier transport capacity of epitaxial layer as a whole;Test obtained is the diffusion length in the direction perpendicular to the surface of epitaxial wafer, is favorable for directly reflecting the carrier transport characteristics of vertical device.

The invention belongs to the technical field of semiconductor material synthesis, and provides a method for realizing h-BN efficient n-type doping and a semiconductor material, graphene is introduced into hexagonal boron nitride as a quantum dot, the two materials form a type-I type band order difference, a local band edge state is formed, the doping energy level and the relative position of a band edge are changed, and the doping efficiency is improved. According to the method, the activation energy of the n-type dopant is compensated by utilizing the band order difference between graphene and an h-BN energy band, the ionization efficiency of doped atoms at the temperature of a working substance is improved, the carrier concentration is increased, the doping efficiency and the conductivity of the h-BN are improved, guidance is provided for realizing an h-BN material with high electron concentration, and the application prospect of the h-BN in power electronic devices is widened.

A method for quality analysis of silicon rods in the photovoltaic silicon wafer production process includes the following steps: resistivity testing of the silicon rods to obtain resistivity values; minority carrier lifetime testing of the silicon rods to obtain minority carrier lifetime values; calculation of the ratio between the minority carrier lifetime and resistivity values, referred to as the relative minority carrier lifetime; calculation of the relative minority carrier lifetime values ​​for a group of silicon rod samples; grouping the samples into m groups based on their relative minority carrier lifetime values, and slicing each group; calculating the average relative minority carrier lifetime value for each of the m groups of samples; evaluating the cell efficiency of each of the m groups of silicon wafer samples to obtain the cell conversion efficiency data for the m groups; and performing correlation analysis between the cell conversion efficiency data and the average relative minority carrier lifetime values ​​of the m groups to verify the correlation between the two sets of data. This invention proposes a method for evaluating silicon rod quality using relative minority carrier lifetime, which can eliminate the influence of doping resistivity on minority carrier lifetime.

This invention discloses a method for measuring the electron drift velocity of a group III nitride heterostructure in multiple physical environments, belonging to the field of semiconductor technology. The method first forms an H-shaped channel in the group III nitride heterostructure and symmetrically prepares rectangular test electrodes on both sides of the channel to obtain the sample to be tested. Then, the sample is placed in one or more physical environments and connected to a test circuit. A voltage is applied to the test electrodes, and the current flowing through the H-shaped channel is measured to obtain the electron drift velocity v. The variation of the electron drift velocity v with the electric field E under external physical environments such as temperature field, light field, magnetic field, and different gas atmospheres is obtained. Measuring the 2DEG electron drift velocity in a group III nitride heterostructure under different physical fields is of great significance for comprehensively evaluating and optimizing the performance of group III nitride devices, providing guidance for device design and optimization.

The invention relates to the technical field of semiconductor testing and metering, and discloses a standard sample carrier lifetime valuing method and traceability system, and the method comprises the following steps: positioning a sample to be tested, stabilizing the environment, and initializing the system; constructing a periodically modulated acoustic potential well in the sample body, and exciting a coherent quantum state at the center of the potential well by using a coherent double-pulse sequence; a returned optical signal is collected, and an attenuation envelope of the returned optical signal is extracted through a differential locking demodulation technology; physical self-consistency verification is carried out through a rotating acoustic field stress axis, and attenuation envelope fitting is carried out to extract carrier life parameters; and performing statistical analysis on the multiple groups of parameters to determine a final constant value, and constructing a quantity value tracing chain to a frequency reference. According to the invention, the three-dimensional acoustic standing wave field is adopted to construct the acoustic potential well in the sample sheet material, and the photon-generated carriers are confined in the sample sheet in a non-contact manner, so that the direct measurement of the carrier body lifetime is realized, and the defect that the measurement result is seriously influenced by the surface state of the sample sheet is overcome.

The invention relates to various devices and methods for preventing the injection of a substrate current into the substrate sub of a CMOS circuit. For this purpose, the devices implement different methods for preventing such injection. They detect the potential of a contact (PDH, PDL) of the integrated CMOS circuit, compare the value of the detected potential with a reference value, and connect the contact (PDH, PDL) to a leakage circuit node (ABK) to drain the current, so that it does not flow through the parasitic bipolar lateral structure, i.e., not into the substrate. The leakage circuit node can be connected, for example, to the reference potential line (GND) or to another line that has a higher potential than that of the reference potential line (GND). This electrical connection is then activated or...initiated when the potential value of the contact (PDH, PDL) is below or equal to a reference value, where this reference value is below the potential value of the substrate Sub and / or below the potential value of the reference potential line (GND) or the other line mentioned above.

The present invention relates to a method for characterizing in pulse mode a III-V semiconductor transistor (2) and to an associated test bed (1), in which method and bed an RF pre-pulse is applied to the gate (2a) of the transistor (2) with a power level NRF defined according to a first predetermined relationship so as to set the state of charge of traps in the transistor (2), then a first DC pulse and a second DC pulse are applied to the gate (2a) and to the drain (2b) of the transistor (2), respectively, the first DC pulse and the second DC pulse having a first DC level N1 and a second DC level N2 defined according to a second predetermined relationship, respectively.

A method of determining electrical characteristics of material local to a specific area of a semiconductor wafer is disclosed. In one embodiment, the method comprises sinking or sourcing current through at least one selected device under test (DUT) on the semiconductor wafer, converting the current sourcing or sinking through the selected DUT (IDUT) into a voltage, comparing the converted voltage against a linear voltage ramp, generating an output clock based on the comparison, and measuring a duty cycle of the output clock. In one embodiment, IDUT is sourced or sinked using regulated drain-to-source voltages (VDS) across the selected DUT, the duty cycle of the output clock dependent on the amount of current sinking or sourcing through the selected DUT, and electrical characteristics of the material local to the specific area of the semiconductor wafer where the DUT is located are determined based on the duty cycle of the output clock.

The invention discloses a wafer film carrier characteristic measurement sample table integrated with a temperature control function, and relates to the technical field of wafer films, the wafer film carrier characteristic measurement sample table comprises a measurement table main body, the outer wall of the measurement table main body is fixedly connected with a temperature control box, and the inner wall of the measurement table main body is fixedly connected with a main body shell; a plurality of bearing assemblies are distributed on the top of the main body shell in an arc-shaped array mode, a plurality of fixing mechanisms are distributed on the outer wall of the main body shell in an arc-shaped array mode, and a hot air mechanism is arranged on the inner wall of the main body shell. According to the wafer film carrier characteristic measurement sample stage integrated with the temperature control function, the fixed mechanism and the hot air mechanism are arranged, and a wafer film-substrate complex as a wafer film carrier characteristic measurement object is directionally heated in a hot air non-contact mode; and a fixing mechanism for fixing the wafer film-substrate complex is in a non-contact mode, so that deformation caused by heating expansion of the clamp is prevented.

A system includes a semiconductor device having a source terminal, a drain terminal, and an interface layer between the source terminal and the drain terminal, the interface layer having a plurality of interface channels. The system also includes a degradation monitoring circuit having an electrical sensor, the degradation monitoring circuit being configured to: generate, using the electrical sensor, a sensor signal corresponding to one or more interface channels of the plurality of interface channels; determine, based on the sensor signal, whether degradation of a material is present at the one or more interface channels of the plurality of interface channels; and output information indicative of whether degradation of the material is present at the one or more interface channels of the plurality of interface channels.

The invention relates to a method and a system for identifying influence of epitaxial wafer defects on performance of a SiC device in the technical field of semiconductors. The method comprises the following steps: acquiring photoluminescence parameters of an epitaxial wafer of the SiC device through NUV-PL scanning; determining a sharp corner direction of the triangular epitaxial wafer defect based on a scanning result of NUV-PL scanning, and determining a step flow direction of the SiC device based on the sharp corner direction; determining a first orientation of the defect of the triangular epitaxial wafer in the SiC device based on the step flow direction, and determining a second orientation of the defect of the triangular epitaxial wafer in the SiC device based on the photoluminescence parameter; obtaining the defect position of the triangular epitaxial wafer based on the first orientation and the second orientation; and obtaining a device performance influence result according to the defect position, thereby solving the problem that the influence degree of the performance of the SiC device influenced by the defect of the epitaxial wafer cannot be judged because the defect position of the epitaxial wafer cannot be identified in the manufacturing process of the existing SiC device.