Apparatus and method for combined micro-scale and nano-scale c-v, q-v, and i-v testing of semiconductor materials
a semiconductor material and micro-scale technology, applied in the direction of individual semiconductor device testing, scanning probe techniques, instruments, etc., can solve the problems of adverse effects on the signal to noise ratio of measurement, adverse effects on the properties of the device to be measured, and reduction of the sampled area, so as to reduce the measurement area and small capacitance variations
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[0040]Referring to the drawings, FIG. 1 shows schematically the elements of a system 10 embodying the invention. A probe 12 is employed for contact with a semiconductor wafer 14 under test. The wafer is supported, by a test plate 16 of a probe station translation stage 18. A position sensor 20 senses the contact by the probe on the semiconductor surface, as will be described in greater detail subsequently. A probe controller 22 such as is disclosed in U.S. Pat. No. 3,345,567 Turner et. al, which is incorporated into this specification by reference can ‘be used to position the probe with respect to the surface of the semiconductor if the structures to be probed are lame enough to be seen optically or if the structure to be probed is uniform such as a semiconductor wafer and precise positioning is not required. If the structure to be probed is too small to be seen with optical microscopes, then a separate means must be employed to locate the feature and position the probe relative to ...
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