222results about "Contactless circuit testing" patented technology

The present application provides a method for performance evaluation and structure optimization of a high-power semiconductor laser chip, and a system for performance evaluation. Wherein the method for performance evaluation of a high-power semiconductor laser chip comprises: setting a window in an N-surface electrode of a chip to be tested; maintaining the chip to be tested in an operating state, wherein spontaneous radiation is generated in an active area of a quantum well of the chip to be tested; imaging the spontaneous radiation at a position outside the chip to be tested; acquiring, by using a spectrometer outside the chip to be tested, a spectrum of the spontaneous radiation to obtain a two-dimensional distribution of temperature of the quantum well of the chip to be tested in the operating state; and acquiring, by using a CCD camera outside the chip to be tested, an image of the spontaneous radiation to obtain a two-dimensional distribution of carriers in the quantum well of the chip to be tested in the operating state. The method for performance evaluation and structure optimization of a high-power semiconductor laser chip provided by the present application can get the temperature distribution and the carrier concentration distribution of the chip to be tested in the operating state with a resolution that is freely adjustable, the operation is convenient and easy to implement, and the accuracy of evaluation results is effectively improved.

The embodiment of the present application discloses a kind of test system and heat dissipation method of pulse laser analog single particle effect, and it is used to improve the heat dissipation efficiency of the chip to be tested for heat dissipation.The heat dissipation system includes pulse laser and heat conduction component.The heat conduction component is located between the pulse laser and the chip to be tested.The heat conduction component includes light-transmitting region and heat-conducting region.The light-transmitting region is physically connected with the heat-conducting region.The pulse laser emitted by the pulse laser is transmitted to the chip to be tested through the light-transmitting region.The pulse laser is used to carry out pulse laser analog single particle effect test on the chip to be tested.The light-transmitting region is physically connected with the chip to be tested.The heat of the chip to be tested is dissipated through the light-transmitting region and the heat-conducting region.

The present invention relates to a device and a method for controlling NV quantum sensor-based automatic detection of a semiconductor wafer micropattern size and a micropattern defect, the device comprising a wafer inspection head module 100, a non-contact wafer micropattern NV quantum-sensing module 200, a stage module 300 for wafer inspection, and an intelligent control module 400, wherein: versatility and adaptability are provided to wafers in various sizes and forms; precise wafer alignment is achieved; the scanning accuracy of the non-contact wafer micropattern NV quantum-sensing module is increased; noise of temperature changes, which affects NV center-based quantum sensing, is removed through a temperature maintenance control unit; and real-time analysis data and automatic correction data about the size, arrangement, and defect state of wafer micropatterns are generated through the intelligent control module.

A bridge beam attached to a semiconductor device handling apparatus that handles a semiconductor device, includes a beam-shaped main body to which a probe card is attached. The probe card has a contact that is electrically connected to a terminal of the semiconductor device. The bridge beam includes a first actuator, attached to the beam-shaped main body, that moves an optical probe relative to the semiconductor device. The optical probe performs one or both of emitting an optical signal to the semiconductor device and receiving the optical signal from the semiconductor device.

Aspects of this disclosure configure a processor for detecting defects in the solder mask of a printed circuit board (PCB) using an optical waveguide. The processor directs an optical beam toward the input of one or more optical waveguides embedded in a protective coating layer of a PCB, the protective coating layer being adjacent to one or more conductive traces of the PCB. The processor measures a beam property of the optical beam emitted by the one or more optical waveguides. The processor detects a break in the optical beam emitted by the one or more optical waveguides based on this beam property.The processor detects a fault in the protective coating layer of the PCB based on detecting the interruption of the optical beam emitted by the one or more optical waveguides.

The invention belongs to the technical field of semiconductor packaging, and provides an online monitoring method and system for thermal cycle failure of TSV copper salient points, and the method comprises the steps: synchronously collecting resistance data and acoustic emission signals of a test structure containing the TSV copper salient points, and writing the resistance data and acoustic emission signals into a data cache region; calculating a resistance change rate relative to an initial value based on the resistance data in the data cache region, and generating a primary trigger event when the resistance change rate exceeds a real-time judgment threshold value; in response to the primary trigger event, estimating physical coordinates of the abnormal activity; scanning the region of interest taking the physical coordinates as the center to obtain local deformation data, and fusing the physical coordinates, the local deformation data and the resistance change rate to generate a failure diagnosis conclusion; and based on the failure diagnosis conclusion, carrying out backtracking analysis on historical data before the primary trigger event occurs in the data cache region, and adaptively adjusting a real-time judgment threshold, so that real-time monitoring and intelligent diagnosis of the TSV copper bump thermal cycle failure are realized.

The application provides a chip loss testing method and a chip loss testing device. The chip loss testing method comprises the following steps: coupling a first optical fiber in a test optical fiber array with an input waveguide of a chip to be tested; coupling a second optical fiber in the test optical fiber array with an output waveguide of the chip to be tested, wherein the number of the second optical fiber is not less than the number of the output waveguide of the chip to be tested; testing a test data set obtained by inputting a first laser into the first optical fiber, passing through the input waveguide of the chip to be tested and the output waveguide of the chip to be tested, and outputting by the second optical fiber, wherein the number of test data in the test data set is the same as the number of the output waveguide of the chip to be tested; and calculating loss data of each channel of the chip to be tested according to test data set and calibration data matched with the test optical fiber array, wherein the input waveguide of the chip to be tested and any one of the output waveguides of the chip to be tested form a channel.

An embodiment of the present disclosure provides a pulse electron microscope device including: a pulse generator configured to emit a laser pulse; a first beam splitter configured to split the laser pulse into a first laser pulse and a second laser pulse; a second beam splitter configured to split the second laser pulse and to reflect a second-1 laser pulse; an interval controller configured to control a time interval between the first laser pulse and the second-1 laser pulse by controlling an optical path length of the first laser pulse; a column part including a photocathode, the photocathode configured to convert the first laser pulse into a first electron pulse and convert the second-1 laser pulse into a second electron pulse; and an inspection module configured to inspect electrical defects in the sample by detecting a change in potential occurring on a surface of the sample.

The present invention relates to an optical coupling module (105) for testing an element (135) to be tested, the optical coupling module (105) comprising a module carrier (107) having a test-signal portion (110) for emitting an optical test signal (125) to a coupling region (130) of the element (135) to be tested or for receiving an optical test signal (125) from the coupling region (130) of the element (135) to be tested, and a camera system (140) fixed to the module carrier (107) for identifying the position of the coupling region (130) of the element (135) to be tested in relation to the module carrier (105).

The purpose of the present disclosure is to provide a technique capable of obtaining, from a language model, an instruction for an evaluation apparatus for evaluating a semiconductor device by inputting a character string into the language model. The method of the present disclosure receives specification data describing an operation specification of an evaluation device from a language model by inputting an instruction for the evaluation device of a semiconductor device to the language model. The language model is finely tuned in advance by at least one of domain knowledge of the semiconductor device and domain knowledge related to the evaluation device.

This analysis device 1 comprises: a tester 10 that inputs a test signal St having a prescribed frequency to a semiconductor device D; an X-ray irradiation device 11 that irradiates the semiconductor device D with X-rays R; a detector 15 that detects X-rays (transmitted X-rays Rt) from the semiconductor device D due to the irradiation with the X-rays R and outputs a detection signal Sd on the basis of the detected result; and a signal processing device 16 that performs, on the detection signal Sd, signal processing based on the prescribed frequency.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

The application provides a chip-scale package interconnection structure failure analysis method and device, comprising: determining the failure external pin corresponding to the failure CSP package interconnection structure according to the current-voltage characteristic curve corresponding to each external pin; collecting and analyzing the time-domain reflection waveform of the failure external pin by using the electro-optical terahertz pulse reflection technology, positioning the target interconnection failure area in the interconnection path where the failure external pin is located according to the amplitude, time delay and waveform distortion characteristics of the reflection pulse; scanning the target interconnection failure area by using the three-dimensional X-ray microscopic imaging technology, and determining the target position of the failure point on the interconnection path where the failure external pin is located and the corresponding structural defects based on the scanning result. The application realizes the non-destructive failure analysis of the CSP package interconnection structure by combining the electro-optical terahertz pulse reflection technology and the three-dimensional X-ray microscopic imaging technology, and improves the failure point fault positioning accuracy and efficiency.

The application discloses a kind of to be measured chip low temperature failure test system and test method, system includes refrigeration module, leakage current acquisition module, image acquisition module and control module;Refrigeration module makes to be measured chip from first temperature state cooling and maintain second temperature state;Image acquisition module obtains the first image information of to be measured chip at first temperature state, second image information at second temperature state;Leakage current acquisition module obtains first leakage current and second leakage current;Control module is electrically connected with image acquisition module and leakage current acquisition module respectively, for capturing first leakage current compound generated first photon, determine the initial bright spot of first photon on first image information;Capture second leakage current compound generated second photon, determine the failure bright spot of second photon on second image information;According to initial bright spot and failure bright spot, determine the failure position of to be measured chip.Using the above system, the failure position of low temperature failure to be measured chip under room temperature is quickly determined.

This inspection device inspects an inspection object which has an imaging device into which light enters from a side opposite a wiring layer. The inspection device includes: a mounting platform through which light can pass that has a mounting surface on which the inspection object is to be mounted in a manner facing the opposite side of the imaging device with respect to the wiring layer; a mounting platform operating part capable of moving the mounting platform vertically and horizontally; and an irradiation device that irradiates inspection light onto the imaging device through the mounting surface. The mounting platform operating part changes, by moving the mounting platform, the relative position of the irradiation device with respect to the inspection object mounted on the mounting surface.

An assembly for monitoring a semiconductor device under test comprising a mill configured to mill the device, a sensor configured to measure an electrical characteristic of the device, and a computer configured to determine the amount of strain in the device from the electrical characteristic when the mill is milling the device and detect an endpoint of milling at a circuit within the device. In use the endpoints of the milling process of the semiconductor device are detected measuring an electrical characteristic of the device with a sensor during milling determining the amount of strain in the device from the electrical characteristic and detecting an endpoint of the milling process within the device based on the amount of strain.

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation while other utilize four wave-mixing or multi-wave mixing. Corona discharge may be applied to the sample to provide additional information. Some approaches involve determining current flow from a sample illuminated with radiation.

The embodiment of the invention discloses a crystal oscillator, device and method for a single particle test. In a specific implementation mode, the crystal oscillator comprises a to-be-radiated chip, a differential chip, a quartz oscillator, a first base and a second base, the to-be-radiated chip is bonded in the cavity of the first base through a conductive adhesive, and the first base exposes the to-be-radiated chip; the differential chip is electrically connected with each port in the cavity of the first base through gold wire bonding; the quartz oscillator is bonded on a wafer placing platform in the cavity of the first base through a conductive adhesive and is electrically connected with the chip to be radiated to form an oscillation loop, and the orthographic projection of the quartz oscillator in the first base is not overlapped with the orthographic projection of the chip to be radiated in the first base; and the first base is mounted on the second base through a conductive adhesive.

An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.

Approaches and probes for excitation, detection, and sensing of samples. An example method includes positioning probes of a test tool relative to contact points that are associated with samples of a sample array such that the probes come into electrical contact with the sample array at the contact points, driving parallel electrical excitation of the samples, where electrical contact between the probes and the contact points is maintained continuously while performing the driving, and the parallel excitation of the samples produces values for testing the samples, and repeating the foregoing one or more times for other contact points. Another example method submerges a probe in a liquid conductive material to provide a conductive liquid at the end of the probe thereof and that can be positioned and / or moved continuously relative to the contact points of a sample to facilitate delivery of an electrical signal to drive excitation of the sample.

The application discloses a microwave chip testing tool, relates to the technical field of microwave chip testing, and aims to solve the technical problem of insufficient function of clamping equipment in the microwave chip testing tool, and comprises a testing machine table; a conveying assembly is arranged on the testing machine table; a basic transfer assembly is arranged on the testing machine table and is located opposite an output end of the conveying assembly; a plurality of auxiliary tables for energizing operation of microwave chips are arranged below the basic transfer assembly; and a clamping assembly for stable and limited positioning of the microwave chip testing operation is arranged on the side of the auxiliary table. Based on the adjustment and setting of the clamping assembly, the clamping assembly has two different clamping modes, i.e., a flexible clamping state and an elastic retaining state, the two different clamping modes are used to simulate the different thermal expansion coefficients of gallium arsenide and gallium nitride microwave chips in the energizing test, and the functionality of the operation is effectively improved.

A system comprising an integrated circuit, including a semiconductor substrate (SB), an interconnection portion located above the substrate and having metal layers (M1-M5) and via and contact layers embedded in an electrically insulating region, as well as contact areas located at the last metal layer of the interconnection portion, and detection means configured to detect the possible presence of at least one type of structural defect (DFT1, DFT2) within at least one zone (ZD) of the interconnection portion located below at least one contact area (PD). Figure for the abstract: Fig 5

The present invention provides a test system and a test method for performing a wireless test on a device under test (500) to obtain electromagnetic radiation performance. The test system includes a support table (100) for supporting the device under test, a plurality of test antennas (200), and a moving mechanism including at least two moving units (300). Each moving unit (300) is provided with a test antenna (200), and the test antennas (200) are arranged to have a predetermined angular interval with respect to the support table (100). The moving mechanism further includes a driving unit for driving the moving unit (300) so that the test antennas (200) reach a plurality of sampling points (600). The sampling points (600) are located at a plurality of different angles with respect to the support table (100), and the angular intervals of the sampling points (600) with respect to the support table (100) are smaller than the predetermined angular intervals.

An analysis device 1 comprises: an LSI tester 3 that inputs a test pattern signal TP to a semiconductor device D and outputs a trigger signal indicating start timing of the test pattern signal TP and a test result signal TR indicating a test result, either Pass or Fail, of the semiconductor device D; an SSPD 13 that detects light emitted from a field of view set on the semiconductor device D and outputs a detection signal; and a processing unit 19 that processes the trigger signal and the detection signal to measure elapsed time from the start timing to the timing of the detection signal, generates light emission timing data indicating the elapsed time, classifies the light emission timing data into either Pass or Fail on the basis of the test result signal TR that is output from the LSI tester 3, and calculates, for each Pass and Fail, a total of frequency of the elapsed time indicating multiple light emission timing data when the test pattern signal TP is repeatedly input.

Method for investigating a semiconductor circuit (2) comprising several semiconductor components (4-6) on a front face (2) of a circuit carrier (3), comprising the steps: - Obtaining image data (7) depicting the semiconductor circuit (1) or a test object (8) produced by machining the circuit carrier (3) of the semiconductor circuit (1) from a rear side (9) opposite the front side (2), and - automatic identification of a function (10) of at least one semiconductor component (4-6) and / or at least one group (11) of semiconductor components (4-6) and / or automatic localization (12) of at least one functional block (13) of the semiconductor circuit (1) implementing a given function and / or at least one contact pad (14) of the circuit carrier (3) in the image data (7) by evaluating the image data (7) using an image processing algorithm (15).

The present invention relates to a system for inspecting and correcting a protective layer deposited on an electronic board, this protective layer being a layer of a tropicalizing varnish comprising an irradiation-curable resin, defined by a real state corresponding to a real geometry and / or a real thickness, this system comprising: - an inspection module, configured to inspect the real state of the protective layer; - a computer unit, comprising recording means configured to store data representative of at least two predetermined states relating to the surface state of the protective layer (a compliant state and a state with excess tropicalizing varnish), and also comprising means for comparing the real geometry and / or the real thickness of the protective layer with the data of the compliant and excess tropicalizing varnish states;- an ablation module, configured to remove at least one area of ​​the protective layer and communicating with the computer unit; and - an irradiation polymerization module for the tropicalization varnish, comprising a device emitting energetic radiation and communicating with the computer unit. The present invention also relates to a method for inspecting and correcting a protective layer deposited on an electronic board and implemented by the above system. Figure for the abstract: 1;

Disclosed herein are devices, systems, and methods for cancelling an internal magnetic field caused by a test signal within a test chamber of a scanning electron microscope (SEM). A compensator device includes a set of one or more wire loops around a test chamber and an amplifier configured to drive a current in each wire loop of the set of one or more wire loops. The compensator device also includes a control circuit configured to adjust, via the amplifier, a corresponding amplitude modulation of the current in each wire loop, wherein the control circuit is configured to adjust the corresponding amplitude modulation based on a test signal within the test chamber.

The invention concerns a measurement system (MS) and an inspection method for detecting a defective bonding interface in a sample substrate (1) comprising at least one element (3) disposed on a support (2). According to the invention, the method comprising: a providing step (S1) of placing the sample substrate (1) in the measurement system (MS), a measuring step (S2) of establishing an inclination map of the exposed surface (1a), an analyzing step (S3) of the inclination map for identifying a zone or zones of the exposed surface whose inclinations deviate by more than a given threshold from the inclination of the reference surface; and a decision step (S4) of detecting the presence of a defective bond between the element (3) and the support (2), depending on the result of the analyzing step (S3).

The invention discloses a laser chip temperature resistance detection table, and belongs to the technical field of chip detection, the laser chip temperature resistance detection table comprises a base, two vertical plates are symmetrically and fixedly installed between the inner walls of the base, guide grooves are formed in the vertical plates, and the guide grooves are designed to be low in the middle and high in the two ends. By arranging the guide groove, the bottom plate, the supporting rods and the top plate, the double-shaft motor drives the rolling wheels to roll along the guide groove, the rolling wheels drive the bottom plate to move synchronously, the bottom plate drives the supporting rods to slide along the sliding sleeves in the moving process, and when the rolling wheels roll to the high positions of the two ends of the guide groove, the supporting rods slide upwards in the sliding sleeves to make the top plate rise; when the rollers return to the lower positions of the middle parts of the guide grooves, the supporting rods slide downwards, so that the top plate descends, the chips are moved out, the chips are transferred in different temperature zones, the complexity of manual taking and switching is reduced, the switching time of the chips in the temperature zones is shortened, and the detection efficiency is improved.