422results about "Contactless circuit testing" patented technology

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

The invention provides a power chip packaging detection method and device, and the method comprises the steps: obtaining a structure image, an infrared thermal imaging frame sequence and a working electrical parameter data set of a target power chip after packaging, and carrying out the layering and regional peak analysis, so as to construct a morphology feature parameter set and a thermal anomaly feature set; inputting the morphology feature parameter set, the thermal anomaly feature set and the working electrical parameter data set into a preset defect identification model to obtain a chip packaging anomaly identification map; and performing hierarchical division and node aggregation on the chip packaging abnormity identification map to obtain a packaging defect type result. By constructing a multi-modal packaging detection system taking a structural image, an infrared thermal imaging frame sequence and a working electrical parameter data set as input, accurate identification of the power chip is realized, the accuracy of packaging defect detection is effectively improved, and the problems of low identification precision and information isolation of an existing detection method are improved.

Performance evaluation and structural optimization methods for a high-power semiconductor laser chip, and a performance evaluation system for a high-power semiconductor laser chip. The performance evaluation method for a high-power semiconductor laser chip comprises: providing a window on an N-side electrode of a chip to be tested (step 1); keeping the chip in an operating state (step 2); allowing a quantum well active region of the chip to generate spontaneous emission, so that the spontaneous emission is imaged outside the chip (step 3); acquiring, by means of a spectrograph, a spectrum of the spontaneous emission outside the chip and obtaining a two-dimensional distribution of a quantum well temperature of the chip in the operating state; and acquiring, by means of a CCD camera, an image of the spontaneous emission imaging outside the chip and obtaining a two-dimensional distribution of charge carriers in the quantum well of the chip in the operating state (step 4). According to the performance evaluation and structural optimization methods for a high-power semiconductor laser chip, the distributions of the temperature and the charge carrier concentration in the quantum well of the chip to be tested in the operating state in which the resolution is freely adjusted can be obtained. Operations of the methods are convenient, and implementation is simple and easy, thereby efficiently improving the accuracy of an evaluation result.

The present application provides a method for performance evaluation and structure optimization of a high-power semiconductor laser chip, and a system for performance evaluation. Wherein the method for performance evaluation of a high-power semiconductor laser chip comprises: setting a window in an N-surface electrode of a chip to be tested; maintaining the chip to be tested in an operating state, wherein spontaneous radiation is generated in an active area of a quantum well of the chip to be tested; imaging the spontaneous radiation at a position outside the chip to be tested; acquiring, by using a spectrometer outside the chip to be tested, a spectrum of the spontaneous radiation to obtain a two-dimensional distribution of temperature of the quantum well of the chip to be tested in the operating state; and acquiring, by using a CCD camera outside the chip to be tested, an image of the spontaneous radiation to obtain a two-dimensional distribution of carriers in the quantum well of the chip to be tested in the operating state. The method for performance evaluation and structure optimization of a high-power semiconductor laser chip provided by the present application can get the temperature distribution and the carrier concentration distribution of the chip to be tested in the operating state with a resolution that is freely adjustable, the operation is convenient and easy to implement, and the accuracy of evaluation results is effectively improved.

The present invention relates to optical coupling between optical components and, more particular, to an optical probe (1) configured for optical testing of at least one micro-optical component (50), to a method for producing an optical probe (1), and to a method for optical testing of at least one micro-optical component (50). The optical probe (1) is comprising: - a probe head (10), wherein the probe head (10) comprises a test component (2); - at least one micro-optical element (20), wherein the micro-optical element (20) is a separate element with regard to the test component (2) and in mechanical contact with the test component (2), wherein the micro-optical element (20) is configured to optically couple light (3) between the test component (2) and the micro-optical component (50), thereby being configured to determine an optical performance of the micro-optical component (50), and wherein the micro-optical element (20) is configured to be operated in an index matching liquid (17).

The embodiment of the present application discloses a kind of test system and heat dissipation method of pulse laser analog single particle effect, and it is used to improve the heat dissipation efficiency of the chip to be tested for heat dissipation.The heat dissipation system includes pulse laser and heat conduction component.The heat conduction component is located between the pulse laser and the chip to be tested.The heat conduction component includes light-transmitting region and heat-conducting region.The light-transmitting region is physically connected with the heat-conducting region.The pulse laser emitted by the pulse laser is transmitted to the chip to be tested through the light-transmitting region.The pulse laser is used to carry out pulse laser analog single particle effect test on the chip to be tested.The light-transmitting region is physically connected with the chip to be tested.The heat of the chip to be tested is dissipated through the light-transmitting region and the heat-conducting region.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

The invention relates to the technical field of chip detection, in particular to an integrated circuit chip detection device which comprises an X-ray detector, a driving motor, a centering assembly, a positioning plate, a reciprocating assembly and a cleaning film. Detection devices are mounted in the X-ray detector, a detection platform is arranged between the detection devices, and a driving cavity is formed in the detection platform; the driving motor is installed on the detection platform, a centering assembly is arranged in front of the driving motor, positioning plates are arranged in the centering assembly, the two positioning plates are installed on the detection platform in a sliding mode, and the driving motor drives the two positioning plates to slide horizontally through the centering assembly to achieve positioning of the integrated circuit chip. A reciprocating assembly is arranged in front of the centering assembly, a cleaning film is arranged on the reciprocating assembly, the centering assembly drives the cleaning film through the reciprocating assembly to clean the integrated circuit chip, the imaging precision of the X-ray detection machine is improved through rotary motion, then the detection efficiency and the detection quality are improved, and missed judgment and misjudgment are avoided.

A method for testing a packaging substrate with at least one electron beam column is described. The packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; flooding at least portions of the vacuum chamber with positive ions and / or negative charges; generating an electric field between one or more electrodes and the packaging substrate, the electric field being configured to accelerate the positive ions or the negative charges towards the substrate; and testing the packaging substrate in the vacuum chamber with at least one electron beam column.

The present invention relates to a device and a method for controlling NV quantum sensor-based automatic detection of a semiconductor wafer micropattern size and a micropattern defect, the device comprising a wafer inspection head module 100, a non-contact wafer micropattern NV quantum-sensing module 200, a stage module 300 for wafer inspection, and an intelligent control module 400, wherein: versatility and adaptability are provided to wafers in various sizes and forms; precise wafer alignment is achieved; the scanning accuracy of the non-contact wafer micropattern NV quantum-sensing module is increased; noise of temperature changes, which affects NV center-based quantum sensing, is removed through a temperature maintenance control unit; and real-time analysis data and automatic correction data about the size, arrangement, and defect state of wafer micropatterns are generated through the intelligent control module.

A bridge beam attached to a semiconductor device handling apparatus that handles a semiconductor device, includes a beam-shaped main body to which a probe card is attached. The probe card has a contact that is electrically connected to a terminal of the semiconductor device. The bridge beam includes a first actuator, attached to the beam-shaped main body, that moves an optical probe relative to the semiconductor device. The optical probe performs one or both of emitting an optical signal to the semiconductor device and receiving the optical signal from the semiconductor device.

The invention provides a positioning method and system applied to soft failure of an advanced process SRAM (Static Random Access Memory). The method comprises the following steps: determining boundary conditions of failure of a chip; performing laser scanning test: scanning pixel points on the chip one by one by using laser under the condition around the boundary condition to excite Pass / Fail state change of the chip, so that a contrast difference is generated between a failure position and a normal position, and a laser scanning image and a contrast image are obtained; and superposing the laser scanning image and the contrast image to find a failure position on the laser scanning image, comparing the laser scanning image with the corresponding layout layer, and positioning a hot spot on the layout layer according to the failure position. According to the invention, the dynamic test of the chip can be realized through the combination of the existing light emission microscope equipment and the test machine, and the laser scanning function of the light emission microscope equipment is combined to actively excite the change of the state of the chip when the chip fails and is in a normal critical state, so that the failure position is positioned. And the yield and the reliability of the advanced integrated circuit SRAM are improved.

Aspects of this disclosure configure a processor for detecting defects in the solder mask of a printed circuit board (PCB) using an optical waveguide. The processor directs an optical beam toward the input of one or more optical waveguides embedded in a protective coating layer of a PCB, the protective coating layer being adjacent to one or more conductive traces of the PCB. The processor measures a beam property of the optical beam emitted by the one or more optical waveguides. The processor detects a break in the optical beam emitted by the one or more optical waveguides based on this beam property.The processor detects a fault in the protective coating layer of the PCB based on detecting the interruption of the optical beam emitted by the one or more optical waveguides.

Apparatus for inspecting electrical circuits including a scanner including at least one multiline Time Delay Integration (TDI) sensor having multiple parallel lines of sensor pixels, the multiple lines being separated from each other by a separation distance along a scanning axis, each of the sensor pixels having a sensor pixel dimension along the scanning axis, a linear displacer providing mutual displacement of the TDI sensor and an electrical circuit to be inspected along the scanning axis and scanning optics directing light reflected from the electrical circuit to the sensor pixels, the scanning optics defining a projection of each sensor pixel onto the electrical circuit, which projection defines the area on the electrical circuit from which light reaches each sensor pixel, each projection having a sensor pixel projection dimension along the scanning axis and an image generator constructing an image from composite output pixels of the TDI sensor.

A method of measuring a delay time of a propagation of a signal in a line in a circuit structure, the method comprises irradiating the line by pulses of a charged particle beam, wherein a pulse repetition frequency of the pulses of the charged particle beam is varied. The method further comprises measuring, for each of the pulse repetition frequencies, a secondary charged particle emission responsive to the irradiating the line by the pulses of the charged particle beam at the respective pulse repetition frequency, and deriving the delay time of the line based on the secondary charged particle emission responsive to the varying of the pulse repetition frequency.

The invention belongs to the technical field of semiconductor packaging, and provides an online monitoring method and system for thermal cycle failure of TSV copper salient points, and the method comprises the steps: synchronously collecting resistance data and acoustic emission signals of a test structure containing the TSV copper salient points, and writing the resistance data and acoustic emission signals into a data cache region; calculating a resistance change rate relative to an initial value based on the resistance data in the data cache region, and generating a primary trigger event when the resistance change rate exceeds a real-time judgment threshold value; in response to the primary trigger event, estimating physical coordinates of the abnormal activity; scanning the region of interest taking the physical coordinates as the center to obtain local deformation data, and fusing the physical coordinates, the local deformation data and the resistance change rate to generate a failure diagnosis conclusion; and based on the failure diagnosis conclusion, carrying out backtracking analysis on historical data before the primary trigger event occurs in the data cache region, and adaptively adjusting a real-time judgment threshold, so that real-time monitoring and intelligent diagnosis of the TSV copper bump thermal cycle failure are realized.

System and method for reflective characterization of an antenna system comprising a plurality of input / output ports The invention relates to a system (300) for reflective characterization of an antenna system (100) comprising a plurality of input / output ports. Such a system comprises a measurement antenna (210) coupled to a network analyzer (220) for measuring a backscatter coefficient from the complex amplitude of an incident wave emitted by the measurement antenna towards the antenna system and the complex amplitude of the backscattered wave received by the measurement antenna. Such a system further comprises a circuit (310) comprising a delay line implemented between a first port and a second port of the plurality of ports.The delay line is configured so that an impulse response estimated from backscattering coefficients comprises a plurality of echoes, called useful echoes, having temporal supports distinct from each other, the useful echoes being associated with physical phenomena distinct from each other contributing to said backscattered wave. ABSTRACT FIGURE: [Fig.3].

A test and measurement probe for measuring an electrical signal in a device under test (DUT) includes a probe body, a sensor head separate from the probe body, one or more transmission optical fibers to convey an optical measurement signal between the probe body and the sensor head, and a pluggable interface between the probe body and the sensor head. The probe body includes an optical source to produce the optical measurement signal, receiver circuitry to receive the optical measurement signal and convert the optical measurement signal to an electrical measurement signal, and a connector to output the electrical measurement signal to a test and measurement instrument. The sensor head includes one or more sensor head optical fibers configured to convey the optical measurement signal to cause the electrical signal in the DUT to modify a polarization state of the optical measurement signal.

The application provides a chip loss testing method and a chip loss testing device. The chip loss testing method comprises the following steps: coupling a first optical fiber in a test optical fiber array with an input waveguide of a chip to be tested; coupling a second optical fiber in the test optical fiber array with an output waveguide of the chip to be tested, wherein the number of the second optical fiber is not less than the number of the output waveguide of the chip to be tested; testing a test data set obtained by inputting a first laser into the first optical fiber, passing through the input waveguide of the chip to be tested and the output waveguide of the chip to be tested, and outputting by the second optical fiber, wherein the number of test data in the test data set is the same as the number of the output waveguide of the chip to be tested; and calculating loss data of each channel of the chip to be tested according to test data set and calibration data matched with the test optical fiber array, wherein the input waveguide of the chip to be tested and any one of the output waveguides of the chip to be tested form a channel.

The invention relates to wafer test equipment, which comprises an electric test assembly, which is arranged on a mounting rack and comprises a telescopic member, a fixed end of the telescopic member is provided with a probe disc, the probe disc is provided with a plurality of probes corresponding to electrode pads of a wafer chip to be tested one by one, the probe disc is provided with a plurality of through holes between the probes, and the through holes are communicated with the probe disc. The telescopic end of the telescopic piece is provided with a suction cup, the suction cup is located below the probe disc, and the suction cup is provided with a plurality of suction rods extending into the through holes; and a light testing assembly. According to the wafer test equipment, the to-be-tested wafer is fixed on the suction rod after the angle and the position of the to-be-tested wafer are adjusted, and then the suction cup is driven to move downwards, so that the probes on the probe disc can be in contact with the metal bonding pads of the chips on the to-be-tested wafer, and electrical performance tests can be simultaneously carried out on all the chips on the wafer through the plurality of probes; and the optical fiber array disc is moved to be positioned on the wafer, so that all chips can be subjected to optical testing at one time, and the testing efficiency of the wafer is greatly improved.

An embodiment of the present disclosure provides a pulse electron microscope device including: a pulse generator configured to emit a laser pulse; a first beam splitter configured to split the laser pulse into a first laser pulse and a second laser pulse; a second beam splitter configured to split the second laser pulse and to reflect a second-1 laser pulse; an interval controller configured to control a time interval between the first laser pulse and the second-1 laser pulse by controlling an optical path length of the first laser pulse; a column part including a photocathode, the photocathode configured to convert the first laser pulse into a first electron pulse and convert the second-1 laser pulse into a second electron pulse; and an inspection module configured to inspect electrical defects in the sample by detecting a change in potential occurring on a surface of the sample.

The present invention relates to an optical coupling module (105) for testing an element (135) to be tested, the optical coupling module (105) comprising a module carrier (107) having a test-signal portion (110) for emitting an optical test signal (125) to a coupling region (130) of the element (135) to be tested or for receiving an optical test signal (125) from the coupling region (130) of the element (135) to be tested, and a camera system (140) fixed to the module carrier (107) for identifying the position of the coupling region (130) of the element (135) to be tested in relation to the module carrier (105).

The application provides a power management chip high-low side driving signal timing optimization method and system. Wherein, the method collects temperature data of the power management chip under switching transient working condition by infrared thermal imaging technology, synchronously obtains three-dimensional temperature field distribution of the surface and internal junction temperature of the packaging layer; based on the spatial continuity of the temperature field, the temperature variation characteristics of the power device area are extracted, and the temperature gradient is converted into the Seebeck voltage by using the thermoelectric material embedded in the hot spot area to construct a dynamic thermoelectric feedback network; the coupling relationship between the hot carrier concentration and the driving signal phase shift is established according to the Seebeck voltage data, the disturbance of the hot carrier mobility change on the MOSFET switching delay is quantified; based on the coupling relationship, the rising / falling edge slope of the gate voltage is adjusted, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The application improves the dynamic response accuracy of the power management chip.

Provided is an inspection apparatus capable of improving the responsiveness of temperature adjustment of a substrate. The inspection apparatus of the present invention includes: a stage capable of placing a substrate; a cooling section that cools the substrate placed on the stage; a probe card having a probe that contacts the substrate to supply power; a light irradiation mechanism that irradiates a surface of the substrate opposite the placement surface with light; and a control section that controls the light irradiation mechanism.

The purpose of the present disclosure is to provide a technique capable of obtaining, from a language model, an instruction for an evaluation apparatus for evaluating a semiconductor device by inputting a character string into the language model. The method of the present disclosure receives specification data describing an operation specification of an evaluation device from a language model by inputting an instruction for the evaluation device of a semiconductor device to the language model. The language model is finely tuned in advance by at least one of domain knowledge of the semiconductor device and domain knowledge related to the evaluation device.

To provide a laser-enhanced voltage contrast system using optical fibers.SOLUTION: A system includes a vacuum chamber with a stage that secures a wafer. Light is directed into an optical fiber from a laser source outside the vacuum chamber. The optical fiber transmits all wavelengths of light from the laser source through the walls of the vacuum chamber and into the vacuum chamber.SELECTED DRAWING: Figure 1

This analysis device 1 comprises: a tester 10 that inputs a test signal St having a prescribed frequency to a semiconductor device D; an X-ray irradiation device 11 that irradiates the semiconductor device D with X-rays R; a detector 15 that detects X-rays (transmitted X-rays Rt) from the semiconductor device D due to the irradiation with the X-rays R and outputs a detection signal Sd on the basis of the detected result; and a signal processing device 16 that performs, on the detection signal Sd, signal processing based on the prescribed frequency.

The present invention relates to optical coupling between optical components, and more particularly, to an optical probe (1) configured for optical testing of at least one micro-optical component (50), a method for producing an optical probe (1), and a method for optical testing of at least one micro-optical component (50). The optical probe (1) comprises:-a probe head (10), wherein the probe head (10) comprises a test assembly (2); -at least one micro-optical element (20), where the micro-optical element (20) is a separate element with respect to the test component (2) and is in mechanical contact with the test component (2), where the micro-optical element (20) is configured to optically couple light (3) between the test component (2) and the micro-optical component (50), thereby being configured to determine an optical property of the micro-optical component (50), and wherein the micro-optical element (20) is configured to operate in an index matching liquid (17).