616results about "Contactless circuit testing" patented technology

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

The invention provides a power chip packaging detection method and device, and the method comprises the steps: obtaining a structure image, an infrared thermal imaging frame sequence and a working electrical parameter data set of a target power chip after packaging, and carrying out the layering and regional peak analysis, so as to construct a morphology feature parameter set and a thermal anomaly feature set; inputting the morphology feature parameter set, the thermal anomaly feature set and the working electrical parameter data set into a preset defect identification model to obtain a chip packaging anomaly identification map; and performing hierarchical division and node aggregation on the chip packaging abnormity identification map to obtain a packaging defect type result. By constructing a multi-modal packaging detection system taking a structural image, an infrared thermal imaging frame sequence and a working electrical parameter data set as input, accurate identification of the power chip is realized, the accuracy of packaging defect detection is effectively improved, and the problems of low identification precision and information isolation of an existing detection method are improved.

The invention discloses a three-temperature test method and device for a semiconductor chip, and relates to the technical field of semiconductor chip testing, and the method comprises the steps: inputting an initialization parameter set into an impedance temperature mapping model, carrying out the phase angle analysis and multi-band feature fusion through a broadband impedance spectrum analysis method, obtaining a chip junction temperature instantaneous value, and carrying out the measurement of the junction temperature instantaneous value. A PID controller is utilized to dynamically compensate a junction temperature instantaneous value of a chip, a fuzzy rule base inference engine is utilized to map the junction temperature instantaneous value into an execution instruction set, the execution instruction set is converted into a bidirectional voltage signal through pulse width modulation, a semiconductor chilling plate is driven to perform bidirectional temperature rise and drop control in a three-temperature environment, and real-time temperature change test data is synchronously acquired. According to the method, the junction temperature instantaneous value of the chip can be more accurately obtained by combining broadband impedance spectroscopy analysis with a multi-band characteristic fusion technology, and meanwhile, the PID controller is combined with the fuzzy rule base inference engine, so that a response can be quickly made under the condition that the temperature is quickly changed, and the response capability is greatly improved.

The invention discloses a probe integrated device and a preparation method and a control method of the probe integrated device. The device comprises a probe array, a silicon electrode substrate, a recording chip bare chip and a rigid printed circuit substrate. The preparation method comprises the following steps: preparing a probe array and a silicon electrode substrate; carrying out balling on the bare chip of the recording chip, aligning the bare chip with one end of the silicon electrode substrate, and inversely mounting the bare chip on the probe array and the silicon electrode substrate to obtain a substrate with the bare chip; and adhering to a rigid printed circuit substrate, and connecting through a metal wire to obtain the probe integrated device. The control method comprises the following steps: acquiring a brain neuron signal; and carrying out amplification and analog-to-digital conversion processing on the cerebral neuron signal to obtain a cerebral neuron digital signal. According to the embodiment of the invention, miniaturization of the device can be promoted, acquisition of high-flux signals is facilitated, and three-dimensional space neurons can be recorded. The probe array can be widely applied to the technical field of probe arrays.

The invention discloses a chip fixing device for a low-light microscope, which relates to the technical field of low-light microscopes and comprises a base, an opening is formed in the base, light-transmitting glass is arranged at the bottom of the opening, a plurality of connecting rods are arranged on the inner wall of the opening in the circumferential direction, clamping blocks are arranged at the ends of the connecting rods, and first elastic pieces are further connected to the connecting rods. The first elastic piece is used for pushing the connecting rod to move towards one side of the center of the opening, first slopes are arranged on the side walls of the clamping blocks, and the multiple first slopes are matched to form a receiving opening. A to-be-detected chip is placed in the receiving opening and pressed towards one side of the light-transmitting glass, the connecting rod slides outwards under the action of the first inclined surface, and the clamping blocks are gradually opened until the chip is clamped among the clamping blocks. And under the action of the first elastic piece, the plurality of clamping blocks can clamp the chip in the opening. According to the chip clamping device, clamping can be completed only by pressing the chip into the receiving opening, and rapid clamping of the chip can be achieved.

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and / or magnetic field biases can be applied to the sample to provide additional information.

Performance evaluation and structural optimization methods for a high-power semiconductor laser chip, and a performance evaluation system for a high-power semiconductor laser chip. The performance evaluation method for a high-power semiconductor laser chip comprises: providing a window on an N-side electrode of a chip to be tested (step 1); keeping the chip in an operating state (step 2); allowing a quantum well active region of the chip to generate spontaneous emission, so that the spontaneous emission is imaged outside the chip (step 3); acquiring, by means of a spectrograph, a spectrum of the spontaneous emission outside the chip and obtaining a two-dimensional distribution of a quantum well temperature of the chip in the operating state; and acquiring, by means of a CCD camera, an image of the spontaneous emission imaging outside the chip and obtaining a two-dimensional distribution of charge carriers in the quantum well of the chip in the operating state (step 4). According to the performance evaluation and structural optimization methods for a high-power semiconductor laser chip, the distributions of the temperature and the charge carrier concentration in the quantum well of the chip to be tested in the operating state in which the resolution is freely adjusted can be obtained. Operations of the methods are convenient, and implementation is simple and easy, thereby efficiently improving the accuracy of an evaluation result.

The present application provides a method for performance evaluation and structure optimization of a high-power semiconductor laser chip, and a system for performance evaluation. Wherein the method for performance evaluation of a high-power semiconductor laser chip comprises: setting a window in an N-surface electrode of a chip to be tested; maintaining the chip to be tested in an operating state, wherein spontaneous radiation is generated in an active area of a quantum well of the chip to be tested; imaging the spontaneous radiation at a position outside the chip to be tested; acquiring, by using a spectrometer outside the chip to be tested, a spectrum of the spontaneous radiation to obtain a two-dimensional distribution of temperature of the quantum well of the chip to be tested in the operating state; and acquiring, by using a CCD camera outside the chip to be tested, an image of the spontaneous radiation to obtain a two-dimensional distribution of carriers in the quantum well of the chip to be tested in the operating state. The method for performance evaluation and structure optimization of a high-power semiconductor laser chip provided by the present application can get the temperature distribution and the carrier concentration distribution of the chip to be tested in the operating state with a resolution that is freely adjustable, the operation is convenient and easy to implement, and the accuracy of evaluation results is effectively improved.

An optical metrology device includes a selectable pump arm that is used to produce a transient response in the target sample and a probe arm and may be configured to perform static Magneto-Optic Kerr Effect (MOKE) measurements or ellipsometry measurements when the pump arm is not selected, and time resolved (TR) MOKE measurements or ellipsometry measurements when the pump arm is selected. The optical metrology device may be further configured to perform opto-acoustic measurements when the pump arm is selected. A pulse shaper in the pump arm may be used to pulse duration, phase, or both, of the incident pump beam to enable measurement of the dependence of the magnetic dynamics on the pump pulse characteristics. The optical metrology device may be configured to operate at a single selectable wavelength or multiple wavelengths in a continuous or discontinuous spectrum.

The present invention relates to optical coupling between optical components and, more particular, to an optical probe (1) configured for optical testing of at least one micro-optical component (50), to a method for producing an optical probe (1), and to a method for optical testing of at least one micro-optical component (50). The optical probe (1) is comprising: - a probe head (10), wherein the probe head (10) comprises a test component (2); - at least one micro-optical element (20), wherein the micro-optical element (20) is a separate element with regard to the test component (2) and in mechanical contact with the test component (2), wherein the micro-optical element (20) is configured to optically couple light (3) between the test component (2) and the micro-optical component (50), thereby being configured to determine an optical performance of the micro-optical component (50), and wherein the micro-optical element (20) is configured to be operated in an index matching liquid (17).

The present invention discloses an experimental apparatus and a test method for a pulse laser irradiation wide bandgap power device. The apparatus includes an optical path coupling system, a circuit test system, a temperature control system, and an interaction control system. According to the present invention, irradiation sensitive region locating, irradiation transient current tests, irradiation sensitive condition tests, and irradiation degradation tests for the wide bandgap power device are implemented, and advantages of convenience in experiments, simple operation, automated tests, comprehensive and accurate test results, and the like are achieved.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

The invention provides a protection method and system based on key signal single particle error state coding characterization, which realizes key signal error state characterization and storage through key signal STMR and error key signal ID number coding and through data frames and control frames, and finally completes error state analysis by using a monitoring unit program in a PS system. And forming a protection decision. According to the invention, the resource overhead and the data transmission bandwidth of the user function circuit can be reduced, the reliability of the user function circuit system realized based on the SoC type FPGA is improved, and the method has applicability and operability for the digital circuit system of the electronic equipment for space navigation.

The invention provides a detection system and method based on terahertz pulse on-chip radiation detection. The detection system and method can be applied to the technical field of terahertz nondestructive detection. The detection system comprises a terahertz pulse radiation unit, a pulse regulation and isolation unit and a terahertz pulse detection unit which are integrated on the same chip, the terahertz pulse radiation unit is used for radiating terahertz detection pulses under the action of the first femtosecond laser pulses; the pulse regulation and isolation unit is used for regulating the terahertz detection pulse input from the first port to be output through the third port and regulating the terahertz reflection pulse input from the third port to be output through the second port; and the terahertz pulse detection unit is connected with the second port and is used for detecting the terahertz reflected pulse to obtain a current signal, so that fault defect detection of the detected sample is realized based on the current signal. According to the detection system, damage to the integrated circuit structure in the detection process is avoided, and the problem of poor fault defect detection accuracy is solved.

A system and method for compensating for thermal drift of a probe device includes monitoring a first temperature of a laser source in a sensor head that receives output electrical signals from a DUT and outputs corresponding optical signals; monitoring a second temperature of a photoreceiver in a probe interface that converts the optical signals to electrical test signals to input to the test instrument; calculating a first value of a first bias voltage; applying the first value of the first bias voltage to the laser source to compensate for thermal drift when the first temperature is within a first predefined temperature range; calculating a second value of a second bias voltage for the photoreceiver; and applying the second value of the second bias voltage to the photoreceiver to compensate for thermal drift when the second temperature is within a second predefined temperature range.

The embodiment of the present application discloses a kind of test system and heat dissipation method of pulse laser analog single particle effect, and it is used to improve the heat dissipation efficiency of the chip to be tested for heat dissipation.The heat dissipation system includes pulse laser and heat conduction component.The heat conduction component is located between the pulse laser and the chip to be tested.The heat conduction component includes light-transmitting region and heat-conducting region.The light-transmitting region is physically connected with the heat-conducting region.The pulse laser emitted by the pulse laser is transmitted to the chip to be tested through the light-transmitting region.The pulse laser is used to carry out pulse laser analog single particle effect test on the chip to be tested.The light-transmitting region is physically connected with the chip to be tested.The heat of the chip to be tested is dissipated through the light-transmitting region and the heat-conducting region.

A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packaging substrate with UV radiation.

The invention provides a semi-automatic probe table type testing device for a packaging device, which is used for carrying out reliability screening and testing on the packaging device, and comprises a probe table main body, a horizontal sliding table, a lifting table, an XY rotary loading platform, a material platform and an electronic video microscope, a lifting table is fixed above the horizontal sliding table, an XY rotary loading platform is placed above the lifting table, a material platform is placed above the XY rotary loading platform, and a packaging device is placed at a pre-calibration position of the material platform; an observation groove is formed in the middle of the top of the probe station main body, probe seats are arranged on the periphery of the observation groove, and probe heads capable of being movably adjusted are arranged on the probe seats; a connecting support is fixed above the top of the probe station body, an electronic video microscope is connected to the connecting support, and a lens of the electronic video microscope faces the observation groove. And through the combination of the horizontal sliding table and the lifting table, the requirements of small-batch and multi-variety rapid testing of packaging devices are met.

The invention relates to the technical field of chip detection, in particular to an integrated circuit chip detection device which comprises an X-ray detector, a driving motor, a centering assembly, a positioning plate, a reciprocating assembly and a cleaning film. Detection devices are mounted in the X-ray detector, a detection platform is arranged between the detection devices, and a driving cavity is formed in the detection platform; the driving motor is installed on the detection platform, a centering assembly is arranged in front of the driving motor, positioning plates are arranged in the centering assembly, the two positioning plates are installed on the detection platform in a sliding mode, and the driving motor drives the two positioning plates to slide horizontally through the centering assembly to achieve positioning of the integrated circuit chip. A reciprocating assembly is arranged in front of the centering assembly, a cleaning film is arranged on the reciprocating assembly, the centering assembly drives the cleaning film through the reciprocating assembly to clean the integrated circuit chip, the imaging precision of the X-ray detection machine is improved through rotary motion, then the detection efficiency and the detection quality are improved, and missed judgment and misjudgment are avoided.

A radio frequency conduction test method and a test system are provided. The test method includes: moving a radio frequency test probe to a first pad of a board so as to allow a test signal on the first pad to be transmitted to the radio frequency test probe and then transmitted to a radio frequency test instrument for a radio frequency conduction test, where the test signal in the radio frequency test probe is transmitted to the radio frequency test instrument via an impedance conversion apparatus and a directional coupler, a straight-through output port of the directional coupler is connected to a first measurement port of the radio frequency test instrument, and a coupling output port of the directional coupler is connected to a second measurement port of the radio frequency test instrument.

The invention belongs to the field of circuit board detection, and provides a circuit board component fault detection system and method. The system comprises an infrared acquisition device, a visible light acquisition device and a processor, and the infrared acquisition device is used for acquiring an infrared thermogram of a circuit board to be detected in a set time period and transmitting the infrared thermogram to the processor; the processor is used for converting the received infrared thermogram of the to-be-tested circuit board in a set time period into a corresponding temperature, and judging whether a fault component exists in the to-be-tested circuit board according to a set temperature threshold value; when it is judged that the fault component exists in the to-be-detected circuit board, a visible light collection device is started, and a visible light image, transmitted by the visible light collection device, of the to-be-detected circuit board is received; and extracting visible light characteristics of the visible light image of the circuit board to be detected, comparing the visible light characteristics of the fault component with normal visible light characteristics, and further judging the fault type of the fault component. The circuit board component fault detection efficiency and accuracy are improved.

A method for testing a packaging substrate with at least one electron beam column is described. The packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; flooding at least portions of the vacuum chamber with positive ions and / or negative charges; generating an electric field between one or more electrodes and the packaging substrate, the electric field being configured to accelerate the positive ions or the negative charges towards the substrate; and testing the packaging substrate in the vacuum chamber with at least one electron beam column.

The present invention relates to a device and a method for controlling NV quantum sensor-based automatic detection of a semiconductor wafer micropattern size and a micropattern defect, the device comprising a wafer inspection head module 100, a non-contact wafer micropattern NV quantum-sensing module 200, a stage module 300 for wafer inspection, and an intelligent control module 400, wherein: versatility and adaptability are provided to wafers in various sizes and forms; precise wafer alignment is achieved; the scanning accuracy of the non-contact wafer micropattern NV quantum-sensing module is increased; noise of temperature changes, which affects NV center-based quantum sensing, is removed through a temperature maintenance control unit; and real-time analysis data and automatic correction data about the size, arrangement, and defect state of wafer micropatterns are generated through the intelligent control module.

The present invention provides a calibration device and corresponding calibration method for calibrating a chuck, and a calibration instrument, including a calibration card (6) attachable to or within an insertion opening (E) of a wafer prober (1), forming a corresponding substantially closed space when the calibration card (6) is attached, calibration temperature probes (60, 61) attached to the calibration card (6), and a chuck (3) for carrying a wafer (4), the chuck (3) being temperature-controlled to a set temperature by a temperature controller (300) and movable in a lateral direction (x, y) and a height direction (z) by a position controller (350), and a temperature probe (60, 61) mounted on or above the surface (O) of the chuck (3). and an evaluation device (600) connectable to the calibration temperature probes (60, 61), the temperature controller (300), and the position controller (350), the evaluation device (600) being configured to calibrate temperature output values ​​of the one or more temperature probes (S1-S9) based on the current temperatures at the various positions detected by the calibration temperature probes (60, 61).

A bridge beam attached to a semiconductor device handling apparatus that handles a semiconductor device, includes a beam-shaped main body to which a probe card is attached. The probe card has a contact that is electrically connected to a terminal of the semiconductor device. The bridge beam includes a first actuator, attached to the beam-shaped main body, that moves an optical probe relative to the semiconductor device. The optical probe performs one or both of emitting an optical signal to the semiconductor device and receiving the optical signal from the semiconductor device.

A semiconductor apparatus examination method includes a step of acquiring a first interference waveform based on signals from a plurality of drive elements according to light from a first light beam spot including the plurality of drive elements in a semiconductor apparatus, a step of acquiring a second interference waveform based on signals from the plurality of drive elements according to light from a second light beam spot having a region configured to partially overlap the first spot and including the plurality of drive elements, and a step of separating a waveform signal for each of the drive elements in the first and second spots based on the first and second interference waveforms.

The invention provides a positioning method and system applied to soft failure of an advanced process SRAM (Static Random Access Memory). The method comprises the following steps: determining boundary conditions of failure of a chip; performing laser scanning test: scanning pixel points on the chip one by one by using laser under the condition around the boundary condition to excite Pass / Fail state change of the chip, so that a contrast difference is generated between a failure position and a normal position, and a laser scanning image and a contrast image are obtained; and superposing the laser scanning image and the contrast image to find a failure position on the laser scanning image, comparing the laser scanning image with the corresponding layout layer, and positioning a hot spot on the layout layer according to the failure position. According to the invention, the dynamic test of the chip can be realized through the combination of the existing light emission microscope equipment and the test machine, and the laser scanning function of the light emission microscope equipment is combined to actively excite the change of the state of the chip when the chip fails and is in a normal critical state, so that the failure position is positioned. And the yield and the reliability of the advanced integrated circuit SRAM are improved.

Aspects of this disclosure configure a processor for detecting defects in the solder mask of a printed circuit board (PCB) using an optical waveguide. The processor directs an optical beam toward the input of one or more optical waveguides embedded in a protective coating layer of a PCB, the protective coating layer being adjacent to one or more conductive traces of the PCB. The processor measures a beam property of the optical beam emitted by the one or more optical waveguides. The processor detects a break in the optical beam emitted by the one or more optical waveguides based on this beam property.The processor detects a fault in the protective coating layer of the PCB based on detecting the interruption of the optical beam emitted by the one or more optical waveguides.

A method of identifying defective electrical connections of a substrate is provided, the substrate having a first surface contact and a first electrical connection extending from the first surface contact through the substrate. The method includes placing the substrate on a stage in a vacuum chamber; charging the first surface contact by directing an electron beam on the first surface contact and detecting secondary electrons emitted from the first surface contact during the charging for determining a secondary electron signal over time; and determining a state information about the first electrical connection depending on an occurrence of a drop or decline in the secondary electron signal. Further described is an apparatus for identifying defective electrical connections of a substrate according to the methods described herein.

Apparatus for inspecting electrical circuits including a scanner including at least one multiline Time Delay Integration (TDI) sensor having multiple parallel lines of sensor pixels, the multiple lines being separated from each other by a separation distance along a scanning axis, each of the sensor pixels having a sensor pixel dimension along the scanning axis, a linear displacer providing mutual displacement of the TDI sensor and an electrical circuit to be inspected along the scanning axis and scanning optics directing light reflected from the electrical circuit to the sensor pixels, the scanning optics defining a projection of each sensor pixel onto the electrical circuit, which projection defines the area on the electrical circuit from which light reaches each sensor pixel, each projection having a sensor pixel projection dimension along the scanning axis and an image generator constructing an image from composite output pixels of the TDI sensor.