26 results about "Voltage contrast" patented technology

This invention belongs to the field of integrated circuit testing and semiconductor manufacturing quality control technology, and discloses an integrated circuit final testing method and system based on dynamic power consumption compensation. The method includes the following steps: acquiring power consumption prediction data for each test vector in the test program; querying a lookup table to obtain the expected voltage drop value corresponding to each test vector; performing feedforward pre-compensation on the supply voltage based on the expected voltage drop value before testing; monitoring the actual voltage at the power supply pin in real time during testing; comparing the actual voltage with the target voltage to generate an error signal; performing feedback fine-tuning compensation on the supply voltage based on the error signal; and collecting the actual voltage drop value under each test vector after testing, iteratively updating the expected voltage drop value of the corresponding test vector in the lookup table based on the deviation between the actual voltage drop value and the corresponding expected voltage drop value. This invention can solve the problems of test misjudgment, low yield, and insufficient test coverage caused by IR drop in traditional testing methods.

Sensitive Dynamic Vision Sensor comprising multiple physical pixels, each comprising: a photoreceptor module configured to amplify and duplicate a voltage representing the detected light; a contrast computation module configured to reset the voltage and to launch events; a first and second pixel memory bits, connected to neighbor pixels to share its voltage; and a switch swr configured to disable the contrast computation module; being the physical pixels arranged as macro pixels, each comprising: a master pixel configured not to share voltage with other pixels and to launch events, and the rest of pixels configured to share its voltage with the master pixel, which launches an event when the combined voltage is over a LR-temporal contrast, and a controller configured to set the rest of pixels: in a LR-region, switch swr is activated, or in a HR-region, switch swr is deactivated, launching events when the voltage is over a HR-temporal contrast.

The invention discloses a medium-voltage line single-phase disconnection fault comprehensive diagnosis method, system and device and a medium, and belongs to the technical field of circuit fault identification, and the method comprises the steps: determining the position of a switch, collecting and processing current data, comparing the current data with a preset rated line voltage, judging whether the voltage meets the requirements, carrying out the disconnection phase confirmation, and carrying out the fault diagnosis. And judging whether the fault is a single-phase broken line fault according to the current and the phase included angle. According to the method, the problem that a disconnection fault is misreported due to single-phase pull-in of a disconnecting link is solved by judging the closing position of the switch, and the angle precision problem caused by small non-disconnection phase current amplitude is considered, the non-disconnection phase current angle criterion is opened only when the non-disconnection phase current is greater than 2A, the disconnection missed judgment risk is reduced, and the accuracy of disconnection is improved. Compared with the situation that the single-phase broken line external fault is difficult to judge by the broken line of the branch line and the load is unbalanced, the judgment method of the single-phase broken line external fault is simple and accurate, the misjudgment and missed judgment risks are smaller, and meanwhile, the more complex broken line situation can be considered.

The invention relates to a combined photocolumn for overflow charging and image formation in voltage contrast wafer inspection. A scanning electron microscope system may include an optoelectronic system and a controller. The optoelectronic system may include: an electron source; and a photocolumn configured to direct the electron beam to the sample. The photocolumn may include: a dual lens assembly; a beam limiting aperture disposed between the first and second lenses of the dual lens assembly; and a detector assembly configured to detect electrons scattered from the sample. In an embodiment, the controller of the scanning electron microscope system may be configured to: cause the optoelectronic system to form an overflow electron beam and perform an overflow scan of the sample with the overflow electron beam; causing the optoelectronic system to form an imaging electron beam and performing an imaging scan of the sample using the imaging electron beam; receiving an image acquired by the detector assembly during the imaging scan; and determining a characteristic of the sample based on the image.

The invention provides a detection method for an interconnection structure, and the method comprises the steps: providing a semiconductor substrate with a to-be-detected interconnection structure, and the interconnection structure comprises an interconnection layer and a through hole interconnection structure electrically connected below the interconnection layer; a grinding process is executed to sequentially remove the interconnection layer and the through hole interconnection structure of the lower part of the interconnection layer so as to expose the surface of the residual through hole interconnection structure; performing a heat treatment on the via interconnect structure to recrystallize and shrink it; electron beam defect scanning is carried out on the shrunk through hole interconnection structure to obtain a contrast image, if a dark voltage contrast image in the contrast image can be obtained, it is judged that the electrical property of the through hole interconnection structure corresponding to the dark voltage contrast image is abnormal, and if the dark voltage contrast image in the contrast image is not obtained, it is judged that the electrical property of the through hole interconnection structure is normal. According to the invention, the detection rate and the detection accuracy of the electrical abnormality of the through hole interconnection structure can be improved.

The invention provides an anomaly detection method and device based on image recognition. The method comprises the following steps: firstly, acquiring brightness information corresponding to contact holes at different positions in a wafer design layout; acquiring an actual voltage contrast image of a contact hole in the wafer, and processing the actual voltage contrast image so as to match the position of the contact hole with a wafer design layout; intercepting a voltage contrast image of each contact hole position, and extracting a gray pixel value of the voltage contrast image of each contact hole; and carrying out brightness difference analysis according to the gray pixel value of the voltage contrast image of each contact hole, and marking the position of the contact hole which does not accord with the brightness information. The abnormal position of the contact hole is detected through the abnormal detection method based on image recognition, difference analysis is quantitatively carried out, the abnormal position can be recognized more accurately, and the accuracy and efficiency of abnormal detection are improved.

The invention provides a voltage contrast anomaly analysis method and device based on image recognition. The voltage contrast anomaly analysis method based on image recognition comprises the steps of firstly intercepting a voltage contrast image of each contact hole in a wafer and extracting a gray pixel value of the voltage contrast image of each contact hole in the wafer; and calculating a distribution histogram of gray pixel values of the voltage contrast images of all the contact holes, obtaining the contact holes with abnormal gray pixel values, and marking the positions of the contact holes with abnormal gray pixel values. According to the invention, the abnormal position of the contact hole is detected through an abnormal analysis method of image recognition, quantitative difference analysis is carried out, the abnormal position of the contact hole can be recognized more accurately, and the accuracy and efficiency of abnormal detection of the contact hole are improved.

A method of determining coordinates of contact through-holes (CTs) in a memory device includes: obtaining a bright voltage contrast (BVC) image including a plurality of CTs in the memory device; converting color components in the BVC image into grayscale values to obtain a grayscale BVC image; performing a dilation process on the grayscale BVC image to obtain a dilated grayscale BVC image; calculating a first threshold for the dilated grayscale BVC image and determining whether the first threshold is greater than or equal to a pre-determined value; in response to the first threshold being greater than or equal to the pre-determined value, performing a first image process on the dilated grayscale BVC image to obtain coordinates of each CT; and in response to the first threshold being smaller than the pre-determined value, performing a second image process on the dilated grayscale BVC image to obtain the coordinates of each CT.

Disclosed are an inspection apparatus and method for inspecting a semiconductor device. The inspection apparatus includes: a stage on which a semiconductor device is disposed; a first light source that irradiates high-frequency light onto an inspection region of the semiconductor device to reduce a potential barrier of a PN junction in the semiconductor device; a beam scanner that is disposed above the semiconductor device and irradiates a charged particle beam onto the inspection region of the semiconductor device to generate secondary electrons; and a defect detector that generates a detection image corresponding to the inspection region and detects a defect image from a plurality of detection images based on a voltage contrast between a reference image and the plurality of detection images, the defect image indicating a defect of the semiconductor device.

Design of voltage contrast (VC) structures and methodology to detect gate end-to-end (ETE) shorts is described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin adjacent to an isolation structure. A first gate electrode is over the vertical stack of horizontal nanowires or the fin. A second gate electrode is on the isolation structure, the second gate electrode along a same direction as the first gate electrode. A dielectric gate plug is between the first gate electrode and the second gate electrode.

Systems and methods of observing a sample using a charged-particle beam apparatus in voltage contrast mode are disclosed. The charged-particle beam apparatus comprises a charged-particle source, an optical source, a charged-particle detector configured to detect charged particles, and a controller having circuitry configured to apply a first signal to cause the optical source to generate the optical pulse, apply a second signal to the charged-particle detector to detect the second plurality of charged particles, and adjust a time delay between the first and the second signals. In some embodiments, the controller having circuitry may be further configured to acquire a plurality of images of a structure, to determine an electrical characteristic of the structure based on the rate of gray level variation of the plurality of images of the structure, and to simulate, using a model, a physical characteristic of the structure based on the determined electrical characteristic.

Systems and methods for implementing charged particle flooding in a charged particle beam apparatus are disclosed. According to certain embodiments, a charged particle beam system includes a charged particle source and a controller which controls the charged particle beam system to emit a charged particle beam in a first mode where the beam is defocused and a second mode where the beam is focused on a surface of a sample.

Sensitive Dynamic Vision Sensor comprising multiple physical pixels, each comprising: a photoreceptor module configured to amplify and duplicate a voltage representing the detected light; a contrast computation module configured to reset the voltage and to launch events; a first and second pixel memory bits, connected to neighbor pixels to share its voltage; and a switch swr configured to disable the contrast computation module; being the physical pixels arranged as macro pixels, each comprising: a master pixel configured not to share voltage with other pixels and to launch events, and the rest of pixels configured to share its voltage with the master pixel, which launches an event when the combined voltage is over a LR-temporal contrast, and a controller configured to set the rest of pixels: in a LR-region, switch swr is activated, or in a HR-region, switch swr is deactivated, launching events when the voltage is over a HR-temporal contrast.

Embodiments described herein may be related to apparatuses, processes, systems, and / or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure. In embodiments, trench contacts (TCN) within a transistor structure may be electrically coupled together with an electrical connection that is electrically isolated from a power rail. In other embodiments, TCN may be electrically coupled using P-type epitaxial layers on a P-type substrate. Other embodiments may be described and / or claimed.

A detection system includes a first electron source configured to generate a first electron beam and to cause the first electron beam to impinge on a sample, a second electron source configured to generate a second electron beam and to cause the second electron beam to impinge on the sample, a detector, and a control system. The control system is configured to control the first electron source to cause the first electron beam to scan an area of the sample, control a charge state of the sample by varying at least one of a landing energy and a beam current of the second electron beam, control the detector to detect electrons emitted by the sample, receive a detector signal from the detector, and generate a voltage contrast image from the detector signal.

Systems and methods of observing a sample using a charged-particle beam apparatus in voltage contrast mode are disclosed. The charged-particle beam apparatus comprises a charged-particle source, an optical source, a charged-particle detector configured to detect charged particles, and a controller having circuitry configured to apply a first signal to cause the optical source to generate the optical pulse, apply a second signal to the charged-particle detector to detect the second plurality of charged particles, and adjust a time delay between the first and the second signals. In some embodiments, the controller having circuitry may be further configured to acquire a plurality of images of a structure, to determine an electrical characteristic of the structure based on the rate of gray level variation of the plurality of images of the structure, and to simulate, using a model, a physical characteristic of the structure based on the determined electrical characteristic.

Disclosed is an improved charged particle beam inspection apparatus, and more particularly, a particle beam inspection apparatus for detecting defects of a thin device structure. The beam inspection apparatus includes: a charged particle beam source for guiding charged particles to a position under inspection of a wafer in a time series; and a controller configured to sample a plurality of images (510-538) of a region of the wafer at different times over a time series. The plurality of images are compared to detect voltage contrast differences or voltage contrast changes (560-564) to identify thin device structure defects (562).

The invention relates to a direct-current fault current clearing strategy suitable for a novel controllable power grid commutation converter. The direct-current fault current clearing strategy comprises the following steps that an energy consumption device is introduced to consume energy for a commutation capacitor; measuring the alternating current side commutation capacitor line voltage, comparing the absolute value of the commutation capacitor line voltage, and selecting the maximum phase of the line voltage; s2, fault current discretization modeling is carried out on the data obtained in the step S2, and the fault current development trend is predicted; s3, according to the discretized fault current model obtained in the step S3, an optimization model is adopted to obtain a switch state signal; s2, carrying out a phase selection straight-through strategy on the line voltage maximum value phase obtained in the step S2, and avoiding an overvoltage phenomenon in a fault clearing process; according to the method, overvoltage of the bridge arm can be effectively avoided, and a feasible solution is provided for a fault ride-through strategy of a direct-current transmission project based on the controllable power grid commutation converter.

The invention relates to a method for rapidly identifying total dose radiation damage of dynamic characteristics of a silicon carbide power transistor. A device involved in the method is composed of an electrostatic test platform, a sample driving board, a driving power supply, a pulse generator, a high-voltage power supply, an oscilloscope and a computer. A drain-source voltage, a drain-source current, a gate-source voltage and a gate voltage of the silicon carbide power transistor are accurately and rapidly measured by using a high-voltage probe on an oscilloscope, and a characteristic curve of the gate-source voltage, the drain-source voltage and gate charges is obtained through calculation. And extracting threshold gate-source charges, gate-source charges, gate-drain charges, gate total charges and Miller voltage of the device according to the IEC60747-9 standard. And comparing gate charge values of the device before and after irradiation, and if degradation is greater than a set pre-value, judging that the dynamic characteristics of the device are subjected to radiation damage. The method is easy and convenient to operate and has certain universality.

The invention provides a method for detecting the open circuit of a through hole in the back-end process of a semiconductor device, and the method comprises the steps: providing a semiconductor wafer which is subjected to a first chemical mechanical polishing technology, and forming an interconnection structure which comprises the through hole and an overlying groove on the semiconductor wafer; performing a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the trench until the top surface of the through hole is exposed; and finally, detecting the processed semiconductor wafer by adopting an electron beam, and determining whether the open circuit defect exists in the through hole or not according to the voltage contrast signal. According to the method, the chemical mechanical polishing process is added once to expose and physically separate the through holes, so that the technical problem that the single open circuit defect of the multi-through-hole redundant structure cannot be detected by the existing electron beam detection is solved, the detection efficiency and the data volume are remarkably improved, and the analysis period of the process problem is shortened.

Systems and methods for implementing charged particle immersion in a charged particle beam device are disclosed. According to particular embodiments, a charged particle beam system includes a charged particle source and a controller that controls the charged particle beam system to emit a charged particle beam in a first mode in which the beam is defocused and in a second mode in which the beam is focused on a surface of a sample.

This application provides a method, apparatus, device, and storage medium for detecting chip anomalies. The method includes: acquiring the basic structure and layering information of the original design layout of the chip to be tested; performing a first calculation logic setting and color characterization on contact holes according to the connection characteristics of the basic structure and a pre-configured observation mode to obtain contact hole layer images; performing a second calculation logic setting and color characterization on each metal layer based on the connection relationship between the contact hole layer, metal layer, and via layer and the contact hole layer image to obtain images of each metal layer; selecting any metal layer as the metal layer to be tested and scanning it using a scanning electron microscope to obtain an actual voltage contrast image; performing image recognition between the metal layer image as a theoretical voltage contrast image and the actual voltage contrast image to obtain a comparison area image; and performing color comparison on the comparison area image to determine anomaly points. The method of this application improves the efficiency of chip anomaly point location.

Systems and methods for determining presence of defects on a sample. Systems and methods may include obtaining a first plurality of images at a first plurality of pixel times of a portion of a wafer at a first beam current, wherein each of the first plurality of images corresponds to a pixel time of the first plurality of pixel times; obtaining a second plurality of images at a second plurality of pixel times of the portion of the wafer at a second beam current that is different from the first beam current, wherein each of the second plurality of images corresponds to a pixel time of the second plurality of pixel times; fitting, with a model, data obtained from the first plurality of images and the second plurality of images; and using the fitted data to analyze the portion of the wafer for determining the presence of any defects.

The present application relates to the technical field of buried layer fault positioning, and particularly relates to a buried layer fault automatic positioning method, comprising: first, obtaining layout data of a to-be-tested chip and a measured voltage contrast atlas; then, extracting layout geometric features and image voltage features, performing image registration to obtain a spatial registration result and establish a unified reference coordinate system; subsequently, circumscribing a voltage abnormal region under the unified reference coordinate system, and determining a corresponding initial candidate network node set; on this basis, obtaining target multi-dimensional physical features, narrowing the region range through joint screening of topology and gradient, and performing physical fault probability modeling to obtain multi-dimensional evaluation indexes of each candidate node; finally, performing fault risk level sorting based on the multi-dimensional evaluation indexes, automatically generating a verification priority and outputting coordinate parameters of a buried layer fault candidate position. The present application realizes precise automatic alignment across dimensional spaces and efficient convergence of fault networks, and significantly improves the accuracy and efficiency of buried layer fault positioning.

Integrated circuit (IC) devices having gate vias adjacent metal contacts over source and drain bodies in transistors.An IC device may include a test structure having a pair of electrodes, a floating electrode and a gate electrode in a dummy transistor, both the floating and gate electrodes adjacent a metal line grounded by the dummy transistor. Voltage contrast analysis (e.g., with e-beam scanning) of a gate via on the floating electrode may be used to detect a via short to the metal line. The test structure may include vast arrays of the electrode pairs.

Systems and methods for inspecting a sample. Systems and methods may include determining a plurality of locations on a sample, each location corresponding to an inspection feature on the sample in a field of view (FOV); providing one or more charged particle beams to the sample, each charged particle beam being provided to a corresponding location of the plurality of locations; for each location, detecting one or more particle emissions caused by the charging of the corresponding location; and for each location, determining defect information of the sample based on the one or more detected particle emissions.