63 results about "Voltage contrast" patented technology

Systems and methods of providing a probe spot in multiple modes of operation of a charged-particle beam apparatus are disclosed. The method may comprise activating a charged-particle source to generate a primary charged-particle beam and selecting between a first mode and a second mode of operation of the charged-particle beam apparatus. In the flooding mode, the condenser lens may focus at least a first portion of the primary charged-particle beam passing through an aperture of the aperture plate to form a second portion of the primary charged-particle beam, and substantially all of the second portion is used to flood a surface of a sample. In the inspection mode, the condenser lens may focus a first portion of the primary charged-particle beam such that the aperture of the aperture plate blocks off peripheral charged-particles to form the second portion of the primary charged-particle beam used to inspect the sample surface.

A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. The bitstream is filtered and decimated to produce an output code representative of the temperature of the chip.

A measurement mark is disclosed. According to certain embodiments, the measurement mark includes a set of first test structures developed in a first layer on a substrate, each of the set of first test structures comprising a plurality of first features made of first conducting material. The measurement mark also includes a set of second test structures developed in a second layer adjacent to the first layer, each of the set of second test structures comprising a plurality of second features made of second conducting material. The measurement mark is configured to indicate connectivity between the set of first test structures and associated second test structures in the set of second test structures when imaged using a voltage-contrast imaging method.

A system and method for defect inspection using voltage contrast in a charged particle system are provided. Some embodiments of the system and method include positioning the stage at a first position to enable a first beam of the plurality of beams to scan a first surface area of the wafer at a first time to generate a first image associated with the first surface area; positioning the stage at a second position to enable a second beam of the plurality of beams to scan the first surface area at a second time to generate a second image associated with the first surface area; and comparing the first image with the second image to enable detecting whether a defect is identified in the first surface area of the wafer.

This invention belongs to the field of integrated circuit testing and semiconductor manufacturing quality control technology, and discloses an integrated circuit final testing method and system based on dynamic power consumption compensation. The method includes the following steps: acquiring power consumption prediction data for each test vector in the test program; querying a lookup table to obtain the expected voltage drop value corresponding to each test vector; performing feedforward pre-compensation on the supply voltage based on the expected voltage drop value before testing; monitoring the actual voltage at the power supply pin in real time during testing; comparing the actual voltage with the target voltage to generate an error signal; performing feedback fine-tuning compensation on the supply voltage based on the error signal; and collecting the actual voltage drop value under each test vector after testing, iteratively updating the expected voltage drop value of the corresponding test vector in the lookup table based on the deviation between the actual voltage drop value and the corresponding expected voltage drop value. This invention can solve the problems of test misjudgment, low yield, and insufficient test coverage caused by IR drop in traditional testing methods.

Sensitive Dynamic Vision Sensor comprising multiple physical pixels, each comprising: a photoreceptor module configured to amplify and duplicate a voltage representing the detected light; a contrast computation module configured to reset the voltage and to launch events; a first and second pixel memory bits, connected to neighbor pixels to share its voltage; and a switch swr configured to disable the contrast computation module; being the physical pixels arranged as macro pixels, each comprising: a master pixel configured not to share voltage with other pixels and to launch events, and the rest of pixels configured to share its voltage with the master pixel, which launches an event when the combined voltage is over a LR-temporal contrast, and a controller configured to set the rest of pixels: in a LR-region, switch swr is activated, or in a HR-region, switch swr is deactivated, launching events when the voltage is over a HR-temporal contrast.

A method of defect detection includes providing a wafer including an insulating layer formed over a conductive layer. An opening is formed in the insulating layer by an etch process. A metal material is deposited in the opening and then etched to form a recess in the insulating layer so that a top surface of the metal material is below a top surface of the insulating layer. The wafer is polished so that the top surface of the metal material and the top surface of the insulating layer are co-planar. The wafer is characterized by electron beam inspection in voltage contrast mode to determine whether a defect of the etch process exists. The defect exists when a VC signal of the opening is below a threshold, and the defect does not exist when the VC signal of the opening is at or above the threshold.

The invention discloses a medium-voltage line single-phase disconnection fault comprehensive diagnosis method, system and device and a medium, and belongs to the technical field of circuit fault identification, and the method comprises the steps: determining the position of a switch, collecting and processing current data, comparing the current data with a preset rated line voltage, judging whether the voltage meets the requirements, carrying out the disconnection phase confirmation, and carrying out the fault diagnosis. And judging whether the fault is a single-phase broken line fault according to the current and the phase included angle. According to the method, the problem that a disconnection fault is misreported due to single-phase pull-in of a disconnecting link is solved by judging the closing position of the switch, and the angle precision problem caused by small non-disconnection phase current amplitude is considered, the non-disconnection phase current angle criterion is opened only when the non-disconnection phase current is greater than 2A, the disconnection missed judgment risk is reduced, and the accuracy of disconnection is improved. Compared with the situation that the single-phase broken line external fault is difficult to judge by the broken line of the branch line and the load is unbalanced, the judgment method of the single-phase broken line external fault is simple and accurate, the misjudgment and missed judgment risks are smaller, and meanwhile, the more complex broken line situation can be considered.

The invention relates to a combined photocolumn for overflow charging and image formation in voltage contrast wafer inspection. A scanning electron microscope system may include an optoelectronic system and a controller. The optoelectronic system may include: an electron source; and a photocolumn configured to direct the electron beam to the sample. The photocolumn may include: a dual lens assembly; a beam limiting aperture disposed between the first and second lenses of the dual lens assembly; and a detector assembly configured to detect electrons scattered from the sample. In an embodiment, the controller of the scanning electron microscope system may be configured to: cause the optoelectronic system to form an overflow electron beam and perform an overflow scan of the sample with the overflow electron beam; causing the optoelectronic system to form an imaging electron beam and performing an imaging scan of the sample using the imaging electron beam; receiving an image acquired by the detector assembly during the imaging scan; and determining a characteristic of the sample based on the image.

The invention provides a detection method for an interconnection structure, and the method comprises the steps: providing a semiconductor substrate with a to-be-detected interconnection structure, and the interconnection structure comprises an interconnection layer and a through hole interconnection structure electrically connected below the interconnection layer; a grinding process is executed to sequentially remove the interconnection layer and the through hole interconnection structure of the lower part of the interconnection layer so as to expose the surface of the residual through hole interconnection structure; performing a heat treatment on the via interconnect structure to recrystallize and shrink it; electron beam defect scanning is carried out on the shrunk through hole interconnection structure to obtain a contrast image, if a dark voltage contrast image in the contrast image can be obtained, it is judged that the electrical property of the through hole interconnection structure corresponding to the dark voltage contrast image is abnormal, and if the dark voltage contrast image in the contrast image is not obtained, it is judged that the electrical property of the through hole interconnection structure is normal. According to the invention, the detection rate and the detection accuracy of the electrical abnormality of the through hole interconnection structure can be improved.

The invention provides an anomaly detection method and device based on image recognition. The method comprises the following steps: firstly, acquiring brightness information corresponding to contact holes at different positions in a wafer design layout; acquiring an actual voltage contrast image of a contact hole in the wafer, and processing the actual voltage contrast image so as to match the position of the contact hole with a wafer design layout; intercepting a voltage contrast image of each contact hole position, and extracting a gray pixel value of the voltage contrast image of each contact hole; and carrying out brightness difference analysis according to the gray pixel value of the voltage contrast image of each contact hole, and marking the position of the contact hole which does not accord with the brightness information. The abnormal position of the contact hole is detected through the abnormal detection method based on image recognition, difference analysis is quantitatively carried out, the abnormal position can be recognized more accurately, and the accuracy and efficiency of abnormal detection are improved.

Systems and methods (400; 700) of detecting a defect (638) in a sample (250) using a charged-particle beam apparatus are disclosed. A method (400; 700) for inspecting a sample (250) using a charged-particle beam apparatus includes causing a region of the sample (250) comprising a plurality of features (632) to be charged to a first polarity, causing the region to switch from the first polarity to a second polarity at a switching condition, the switching condition comprising a switching dosage of primary charged particles, forming an inspection image of the region from signal charged particles generated upon interaction of the switching dosage of primary charged particles with the plurality of features (632), and determining whether a feature (632) of the plurality of features (632) is defective based on a gray level value of the feature (632) in the inspection image.

The invention discloses a deep trench capacitor structure failure analysis method and system, and the method comprises the steps: carrying out the grinding of the section of a trench of a DTC device through the combination of voltage contrast and a plane grinding technology, enabling the cross section to become smooth and flat, opening the section of the deep trench, providing an ideal sample surface for the subsequent electron beam absorption current in the deep trench, and improving the detection precision. The nanoprobe is adopted to directly test a current path, and a failure position which cannot be represented in a deep groove device or a material in the prior art in a traditional method can be effectively positioned, so that the failure representation rate is greatly improved, and the problem that the deep defect of the deep groove cannot be positioned in the traditional method is solved.

The invention provides a voltage contrast anomaly analysis method and device based on image recognition. The voltage contrast anomaly analysis method based on image recognition comprises the steps of firstly intercepting a voltage contrast image of each contact hole in a wafer and extracting a gray pixel value of the voltage contrast image of each contact hole in the wafer; and calculating a distribution histogram of gray pixel values of the voltage contrast images of all the contact holes, obtaining the contact holes with abnormal gray pixel values, and marking the positions of the contact holes with abnormal gray pixel values. According to the invention, the abnormal position of the contact hole is detected through an abnormal analysis method of image recognition, quantitative difference analysis is carried out, the abnormal position of the contact hole can be recognized more accurately, and the accuracy and efficiency of abnormal detection of the contact hole are improved.

The present invention discloses a method for analyzing dislocation failure of a read-only memory, comprising: step 1, peeling off all back-end metal wire layers of the read-only memory and exposing the contact hole surface. Step 2, selecting a first cutting area outside a failure module and cutting to form a first groove extending in the column direction, the side of each row of polysilicon strips is exposed on the side of the first groove, and the first groove also exposes the surface of the semiconductor substrate. Step 3, forming a first metal layer on the inner surface of the first groove, the first metal layer makes each row of polysilicon strips and the semiconductor substrate contact and grounded. Step 4, performing voltage contrast imaging and forming a first voltage contrast image, in which the grounded polysilicon strips form a bright image, and the drain contact hole of a storage unit with a normal structure forms a dark image, and the storage unit whose image of the drain contact hole is a bright image is located as a dislocation failure position in the failure module. The present invention can quickly locate the dislocation failure position through the voltage contrast image.

Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, a circuit structure includes an inter-layer dielectric (ILD) layer. A plurality of unidirectional wires is in the ILD layer. In one specific example, the integrated circuit structure includes one or more additional wires in the ILD layer, the one or more additional wires along a direction different than a direction of the plurality of unidirectional wires, and the one or more additional wires are each continuous with a corresponding one of the plurality of unidirectional wires at a location between ends of the corresponding one of the plurality of unidirectional wires. In another specific example, one or more of the plurality of unidirectional wires have a line width transition therein.

Compact semiconductor manufacturing patterning process assessment (e.g., inspection, metrology, and / or other) systems and methods are described. For example, compact metrology systems for sensing multiple wavelengths and / or polarizations of diffracted radiation in parallel are described. These metrology systems may be configured for determining alignment and / or other semiconductor patterning process metrics. As another example, compact assessment systems configured to output multiple wavelengths of radiation in combination with charged particle beams (e.g., electron beams) are also described. These assessment systems may be used in voltage contrast defect inspection operations and / or other assessments. The assessment and / or metrology systems include a compact optical component comprising one or more planar photonic integrated circuits configured to emit (assessment systems) or receive (metrology systems) radiation. This optical component is used to form a significantly more compact assessment and / or metrology system, and / or has other advantages compared to prior systems.

A method of determining coordinates of contact through-holes (CTs) in a memory device includes: obtaining a bright voltage contrast (BVC) image including a plurality of CTs in the memory device; converting color components in the BVC image into grayscale values to obtain a grayscale BVC image; performing a dilation process on the grayscale BVC image to obtain a dilated grayscale BVC image; calculating a first threshold for the dilated grayscale BVC image and determining whether the first threshold is greater than or equal to a pre-determined value; in response to the first threshold being greater than or equal to the pre-determined value, performing a first image process on the dilated grayscale BVC image to obtain coordinates of each CT; and in response to the first threshold being smaller than the pre-determined value, performing a second image process on the dilated grayscale BVC image to obtain the coordinates of each CT.

The embodiment of the invention relates to the technical field of new energy grid-connected testing, and provides an automatic testing method for new energy fault ride-through and related products, and the method comprises the steps: obtaining an impedance partial voltage value of a preset partial voltage impedance circuit according to a preset fault voltage value during voltage fault ride-through and a short-circuit impedance value of a system impedance circuit; acquiring an actual fault moment voltage value of the new energy grid-connected point; according to the fault voltage set value and the actual fault moment voltage value, a voltage comparison error is obtained; if the voltage comparison error is smaller than or equal to the preset threshold value, the impedance voltage division value of the preset voltage division impedance circuit is kept unchanged, and the next preset fault working condition is tested; and if the voltage comparison error is greater than the preset threshold value, adjusting the impedance voltage division value of the preset voltage division impedance circuit, and returning to the step of determining the fault triggering moment. According to the embodiment of the invention, the fault ride-through automatic test based on the impedance voltage division method can be realized, and the fault accuracy and the test efficiency are effectively improved.

The invention provides a test structure and a test method convenient for positioning a short-circuit position of a metal connecting wire. The test structure comprises a snakelike structure, a comb-shaped structure, PN nodes, a first bonding pad and a second bonding pad, the snakelike structure comprises a plurality of long metal wires located on the nth metal layer and a plurality of (n-1) th metal wires located on the (n-1) th metal layer, the snakelike structure is connected with the PN node, and the snakelike structure is connected with the first bonding pad; the comb-shaped structure comprises a comb handle metal wire and a plurality of groups of short metal wires which are positioned on the nth metal layer, and further comprises a plurality of comb tooth metal wires positioned on the (n + 1) th metal layer, all the comb tooth metal wires are respectively connected with the comb handle metal wire, each group of short metal wires are arranged along the corresponding comb tooth metal wire, each short metal wire is connected with the comb tooth metal wire, and each group of short metal wires is connected with the corresponding comb tooth metal wire. The comb-shaped structure is connected with the second bonding pad; and the long metal wires and the short metal wires are staggered. According to the method, whether short circuit exists on the Mn layer or not can be rapidly judged, then the short circuit position can be locked through the voltage contrast method, the process monitoring requirement can be met, and follow-up failure analysis can be facilitated.

Disclosed are an inspection apparatus and method for inspecting a semiconductor device. The inspection apparatus includes: a stage on which a semiconductor device is disposed; a first light source that irradiates high-frequency light onto an inspection region of the semiconductor device to reduce a potential barrier of a PN junction in the semiconductor device; a beam scanner that is disposed above the semiconductor device and irradiates a charged particle beam onto the inspection region of the semiconductor device to generate secondary electrons; and a defect detector that generates a detection image corresponding to the inspection region and detects a defect image from a plurality of detection images based on a voltage contrast between a reference image and the plurality of detection images, the defect image indicating a defect of the semiconductor device.

The invention relates to a semiconductor test structure and a preparation method thereof, and a test device, and relates to the technical field of integrated circuits, the semiconductor test structure comprises a substrate, a source electrode test plug and a drain electrode test plug; the N well region of the substrate internally comprises at least two P-type doped regions which are arranged at intervals; the top surface of the N well region between two adjacent P-type doped regions comprises a grid electrode; in two adjacent P-type doped regions, one P-type doped region is electrically connected with the source test plug, and the other P-type doped region is electrically connected with the drain test plug; wherein the source electrode test plug and the drain electrode test plug are used for acquiring an electron beam detection voltage comparison diagram, and the voltage comparison diagram comprises bright voltage comparison and / or dark voltage comparison used for indicating whether defects exist or not. At least the electron beam detection voltage comparison diagram can be utilized to timely and simply detect whether the NMOS transistor has the open circuit defect or not.

The invention provides a test structure, a failure positioning method and a failure analysis method, which are applied to the field of semiconductor production. According to the manufacturing method, the metal silicide layer is formed on the first active region, and meanwhile, the metal silicide layer is not formed on the second active region, so that the contact plugs in the first active region and the second active region in a normal state have brightness difference in a voltage contrast image; therefore, the short-circuit point is positioned through the brightness difference of the contact plug in the voltage contrast image, and compared with an existing test structure, when failure positioning is carried out, positioning is more accurate, and the workload is smaller.

Systems and methods (400; 700) for detecting defects (638) in a sample (250) using a charged particle beam device are disclosed. A method (400; 700) for inspecting a sample (250) using a charged particle beam device comprises the steps of: causing a region of the sample (250) including a plurality of features (632) to be charged to a first polarity; causing the region to be switched from the first polarity to a second polarity under a switching condition—the switching condition includes the switching capacity of primary charged particles—; forming an inspection image of the region from signal charged particles generated upon interaction between the plurality of features (632) and the switching capacity of primary charged particles; and determining whether there is a defect in the feature (632) of the plurality of features (632) based on the gray level value of the feature (632) in the inspection image.

Design of voltage contrast (VC) structures and methodology to detect gate end-to-end (ETE) shorts is described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin adjacent to an isolation structure. A first gate electrode is over the vertical stack of horizontal nanowires or the fin. A second gate electrode is on the isolation structure, the second gate electrode along a same direction as the first gate electrode. A dielectric gate plug is between the first gate electrode and the second gate electrode.

Systems and methods of observing a sample using a charged-particle beam apparatus in voltage contrast mode are disclosed. The charged-particle beam apparatus comprises a charged-particle source, an optical source, a charged-particle detector configured to detect charged particles, and a controller having circuitry configured to apply a first signal to cause the optical source to generate the optical pulse, apply a second signal to the charged-particle detector to detect the second plurality of charged particles, and adjust a time delay between the first and the second signals. In some embodiments, the controller having circuitry may be further configured to acquire a plurality of images of a structure, to determine an electrical characteristic of the structure based on the rate of gray level variation of the plurality of images of the structure, and to simulate, using a model, a physical characteristic of the structure based on the determined electrical characteristic.

This invention discloses a semiconductor device testing method, a semiconductor device, and a three-dimensional memory. The semiconductor device includes a memory array region and a non-memory array region. The memory array region includes a substrate and multiple channel vias penetrating the substrate. A test block is disposed within the non-memory array region. The test block includes a test substrate that is longitudinally aligned with the substrate and test vias penetrating the test substrate. The test substrate includes multiple longitudinally spaced test semiconductor layers, each with a different volume. A test conductive layer is provided on the sidewall of the test via, and the test conductive layer is conductive to the test semiconductor layer that the bottom of the test via passes through or falls into. The method includes: applying an electric field to the semiconductor device to detect the voltage contrast of the test vias; and determining whether the extension depth of the channel vias is abnormal based on the voltage contrast. This invention avoids the use of destructive testing methods to detect the extension depth of channel vias and improves testing efficiency.

The invention provides a chip abnormity detection method and device, equipment and a storage medium. The method comprises the following steps: acquiring a layout basic structure and hierarchical information in an original design layout of a chip to be detected; according to the connection characteristics of the basic structure and a pre-configured observation mode, performing first computational logic setting and color representation on the contact hole to obtain a contact hole layer image; based on the connection relation of the contact hole layer, the metal layer and the through hole layer and the contact hole layer image, performing second computational logic setting and color representation on each metal layer to obtain each metal layer image; any metal layer is selected as a to-be-detected metal layer, and a scanning electron microscope is adopted for scanning to obtain an actual voltage contrast image; taking the metal layer image as a theoretical voltage contrast image and carrying out image identification on the theoretical voltage contrast image and the actual voltage contrast image so as to obtain a to-be-compared region image; and carrying out color comparison on the to-be-compared area image to determine an abnormal point. According to the method provided by the invention, the chip abnormal point positioning efficiency is improved.

Systems and methods for implementing charged particle flooding in a charged particle beam apparatus are disclosed. According to certain embodiments, a charged particle beam system includes a charged particle source and a controller which controls the charged particle beam system to emit a charged particle beam in a first mode where the beam is defocused and a second mode where the beam is focused on a surface of a sample.

Sensitive Dynamic Vision Sensor comprising multiple physical pixels, each comprising: a photoreceptor module configured to amplify and duplicate a voltage representing the detected light; a contrast computation module configured to reset the voltage and to launch events; a first and second pixel memory bits, connected to neighbor pixels to share its voltage; and a switch swr configured to disable the contrast computation module; being the physical pixels arranged as macro pixels, each comprising: a master pixel configured not to share voltage with other pixels and to launch events, and the rest of pixels configured to share its voltage with the master pixel, which launches an event when the combined voltage is over a LR-temporal contrast, and a controller configured to set the rest of pixels: in a LR-region, switch swr is activated, or in a HR-region, switch swr is deactivated, launching events when the voltage is over a HR-temporal contrast.