3332 results about "Resistive element" patented technology

An inherently tuned antenna has a circuit for harvesting energy transmitted in space and includes portions that are structured to provide regenerative feedback into the antenna to produce an inherently tuned antenna which has an effective area substantially greater than its physical area. The inherently tuned antenna includes inherent distributive inductive, inherent distributive capacitive and inherent distributive resistive elements which cause the antenna to resonate responsive to receipt of energy at a particular frequency and to provide feedback to regenerate the antenna. The circuit may be provided on an integrated circuit chip. An associated method is provided.

An impedance model of tissue is useful for describing conductivity reconstruction in tissue. Techniques for determining and mapping conductivity distribution in tissue supply useful information of anatomical and physiological status in various medical applications. Electrical Impedance Tomography (EIT) techniques are highly suitable for analyzing conductivity distribution. Electrical characteristics of tissue include resistive elements and capacitive elements. EIT techniques involve passing a low frequency current through the body to monitor various anatomical and physiological characteristics. The system can interrogate at multiple frequencies to map impedance. Analytical techniques involve forward and inverse solutions to boundary value analysis to tissue characteristics.

Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.

A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.

The display comprises an array of pixel circuits each comprising an emitter 1 in series with a current modulation transistor, and at least one address circuit, which integrates, for each column, a differential amplifier and a passive element preferably a resistive element, which cooperate with the current modulation transistors so as to form, during address phases in which the emitters are switched “out of the circuit”, a voltage-programmable current generator. After the address phases, thanks to a suitable switch, the emitters are switched “into the circuit” and supplied with the preprogrammed current. Such a display allows the image display quality to be inexpensively improved.

Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.

To provide a resistance element having an electric resistance body with excellent stability and a method of manufacturing the same. The resistance element includes an electric resistance body, on a base body surface, consisting of a carbon nanotube structure layer 14, which configures a mesh structure in which at least plural carbon nanotubes are cross-linked to one another. The method of manufacturing the resistance element includes: an applying step of applying the base body surface 12 with a liquid solution containing carbon nanotubes having functional groups; and a cross-linking step of forming the carbon nanotube structure layer 14, used as an electric resistance body, that configures a mesh structure in which the plural carbon nanotubes are cross-linked to one another through curing of the liquid solution after application.

A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.

Lapping guides for use in fabrication of a magnetic recording head are provided. The lapping guides comprise a first differential electronic lapping guide (ELG) disposed in a first layer of the magnetic recording head. The first differential ELG has a first resistive element and a second resistive element between which is disposed a first common electrical lead. The lapping guides further comprise a second differential ELG disposed in a second layer of the magnetic recording head. The second differential ELG has a third resistive element and a fourth resistive element between which is disposed a second common electrical lead. The first and second differential ELGs share a common ground and a common current injection source. Remaining lapping distances at the first and second layers of the magnetic recording head are determined by measuring changing voltages across the first, second, third and fourth resistive elements, respectively.

A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

An electro-resistance element that develops less leakage and fewer associated short-circuits even when an electro-resistance layer is made thinner, a method of manufacturing the same and an electro-resistance memory using the same are provided. The electro-resistance element includes a first electrode, a second electrode, an electro-resistance layer stacked between the first and the second electrodes and an insulating layer (a tunnel barrier layer). The tunnel barrier layer has a thickness in a range from 0.5 nm to 5 nm both inclusive. The electro-resistance layer is a layer having a plurality of states in which electric resistance values are different and being switchable between the states by applying a voltage or a current between the first and the second electrodes. The electro-resistance layer contains transition metal oxide as its main component.

A self-limiting electrosurgical return electrode for use with electrosurgery. Through the selection of impedance characteristics for the electrode materials of the principal body of the electrode, and through tailoring of electrode geometries, the return electrode of the present invention is self-regulating and self-limiting as to current density and temperature rise so as to prevent patient trauma. The electrosurgical return electrode includes a sheet of material having an effective bulk impedance equal to or greater than about 4,000 OMEGA.cm and one or more connectors for making electrical connection to the sheet. The effective bulk impedance of the sheet may arise from resistive components, capacitive components, inductive components, or combinations thereof. The configuration of the presently described return electrode allows the electrode to self-limit the electrode's current densities, thereby preventing burning of a patient during surgery. Furthermore, through employment of washable surface areas, the electrode is made readily cleanable, disinfectable, sterilizable, and reusable. An optional sleeve is provided for cooperative use with the electrode.

A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2ⁿ (n>1) distinct resistance levels to store n-bit data, at least 2ⁿ−1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.

Biosensor circuit arrangement including a substrate, a sensor element formed in or on a surface region of the substrate with a physical parameter, which is coupled to a substance to be examined, the type of coupling having a resistive component, the sensor element having an electrically conductive sensor electrode that is coupled to the substance to be examined, the sensor element having a measuring transistor the gate terminal of which is coupled to the electrically conductive sensor electrode, and the physical parameter being the threshold voltage of the measuring transistor, and a calibration device formed in or on the substrate, the calibration device being set up such that it is used to at least partly compensate for an alteration of the value of the physical parameter of the sensor element.

A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.

A semiconductor memory device includes memory cells, first wirings, a first current driver circuit, and a second current driver circuit. The memory cell includes a magneto-resistive element having a first ferromagnetic film, an insulating film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the insulating film. The first wiring is provided in close proximity to and insulated from the magneto-resistive element. The first current driver circuit supplies a first current to the first wiring in a write operation to produce a magnetic field around the magneto-resistive elements. The second current driver circuit supplies a second current between the first and second ferromagnetic films via the insulating film in a write and a read operation.

A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure.

A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed through the first and second insulation films, and a plug for electrical connection to the upper electrode film is formed in the via hole. To form the via hole, the first insulation film made of silicon nitride is used as an etching stopper to perform dry etching on the second insulation film. Then, dry etching is performed on the first insulation film to expose the upper electrode film from the via hole.